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DM81LS97A Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer DM81LS97A
Beschreibung (DM81LS95A - DM81LS97A) 3-STATE Octal Buffer
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 7 Seiten
DM81LS97A Datasheet, Funktion
www.DataSheet4U.com
September 1991
Revised May 1999
DM81LS95A • DM81LS96A • DM81LS97A
3-STATE Octal Buffer
General Description
These devices provide eight, two-input buffers in each
package. All employ low-power-Schottky TTL technology.
One of the two inputs to each buffer is used as a control
line to gate the output into the high-impedance state, while
the other input passes the data through the buffer. The
DM81LS95A and DM81LS97A present true data at the out-
puts, while the DM81LS96A is inverting. On the
DM81LS95A and DM81LS96A versions, all eight 3-STATE
enable lines are common, with access through a 2-input
NOR gate. On the DM81LS97A version, four buffers are
enabled from one common line, and the other four buffers
are enabled form another common line. In all cases the
outputs are placed in the 3-STATE condition by applying a
high logic level to the enable pins.
Features
s Typical power dissipation
DM81LS95A, DM81LS97A 80 mW
DM81LS96A
s Typical propagation delay
65 mW
DM81LS95A, DM81LS97A 15 ns
DM81LS96A
10 ns
s Low power-Schottky, 3-STATE technology
Ordering Code:
Order Number Package Number
Package Description
www.DataSheet4U.comDM81LS95AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM81LS95AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM81LS96AWM
DM81LS96AN
DM81LS97AN
M20B
N20A
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
DM81LS95A and DM92LS96A
Pin Names
Descriptions
A1–A8
Y1–Y8
Inputs
Outputs
G1–G2
Active LOW Output Enables (Note 1)
Note 1: Both G1 and G2 must be LOW for outputs to be enabled.
DM81LS97A
Pin Names
Descriptions
A1–A8
Inputs
Y1–Y8
Outputs
G1 Active LOW Output Enable (Y1–Y4)
G2 Active LOW Output Enable (Y5–Y8)
© 1999 Fairchild Semiconductor Corporation DS006435
www.fairchildsemi.com
www.DataSheet4U.com






DM81LS97A Datasheet, Funktion
www.DataSheet4U.com
Physical Dimensions inches (millimeters) unless otherwise noted
www.DataSheet4U.com20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
www.fairchildsemi.com
6
www.DataSheet4U.com

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