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EPF6016 Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EPF6016
Beschreibung (EPF6000 Series) Programmable Logic Device
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 30 Seiten
EPF6016 Datasheet, Funktion
www.DataSheet4U.com
March 2001, ver. 4.1
®
FLEX 6000
Programmable Logic
Device Family
Data Sheet
Features...
s Provides an ideal low-cost, programmable alternative to high-
volume gate array applications and allows fast design changes
during prototyping or design testing
s Product features
– Register-rich, look-up table- (LUT-) based architecture
– OptiFLEX® architecture that increases device area efficiency
Typical gates ranging from 5,000 to 24,000 gates (see Table 1)
Built-in low-skew clock distribution tree
100% functional testing of all devices; test vectors or scan chains
are not required
s System-level features
In-circuit reconfigurability (ICR) via external configuration
device or intelligent controller
5.0-V devices are fully compliant with peripheral component
interconnect Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic
MultiVoltTM I/O interface operation, allowing a device to bridge
between systems operating at different voltages
Low power consumption (typical specification less than 0.5 mA
in standby mode)
3.3-V devices support hot-socketing
Table 1. FLEX 6000 Device Features
Feature
EPF6010A
EPF6016
EPF6016A
EPF6024A
Typical gates (1)
10,000
16,000
16,000
24,000
mLogic elements (LEs)
880
1,320
1,320
1,960
oMaximum I/O pins
102 204 171 218
.cSupply voltage (VCCINT)
3.3 V
5.0 V
3.3 V
3.3 V
UNote:
t4(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.
ataSheeAltera Corporation
www.DA-DS-F6000-04.1
1






EPF6016 Datasheet, Funktion
www.DataSheet4U.com
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 1. OptiFLEX Architecture Block Diagram
IOEs
Row FastTrack
Interconnect
Row FastTrack
Interconnect
IOEs Column FastTrack
Interconnect
Column FastTrack
Interconnect
Local Interconnect
(Each LAB accesses
two local interconnect
areas.)
Logic Elements
FLEX 6000 devices provide four dedicated, global inputs that drive the
control inputs of the flipflops to ensure efficient distribution of high-
speed, low-skew control signals. These inputs use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect. These inputs can also be driven by internal logic, providing
an ideal solution for a clock divider or an internally generated
masynchronous clear signal that clears many registers in the device. The
.codedicated global routing structure is built into the device, eliminating the
need to create a clock tree.
t4ULogic Array Block
e An LAB consists of ten LEs, their associated carry and cascade chains, the
e LAB control signals, and the LAB local interconnect. The LAB provides
h the coarse-grained structure of the FLEX 6000 architecture, and facilitates
S efficient routing with optimum device utilization and high performance.
www.Data6 Altera Corporation

6 Page









EPF6016 pdf, datenblatt
www.DataSheet4U.com
FLEX 6000 Programmable Logic Device Family Data Sheet
Cascade Chain
The cascade chain enables the FLEX 6000 architecture to implement very
wide fan-in functions. Adjacent LUTs can be used to implement portions
of the function in parallel; the cascade chain serially connects the
intermediate values. The cascade chain can use a logical AND or logical
OR gate (via De Morgans inversion) to connect the outputs of adjacent
LEs. Each additional LE provides four more inputs to the effective width
of a function, with a delay as low as 0.5 ns per LE. Cascade chain logic can
be created automatically by the Altera software during design processing,
or manually by the designer during design entry. Parameterized functions
such as LPM and DesignWare functions automatically take advantage of
cascade chains for the appropriate functions.
A cascade chain implementing an AND gate can use the register in the last
LE; a cascade chain implementing an OR gate cannot use this register
because of the inversion required to implement the OR gate.
Because the first LE of an LAB can generate control signals for that LAB,
the first LE in each LAB is not included in cascade chains. Moreover,
cascade chains longer than nine bits are automatically implemented by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from an even-numbered LAB to another even-numbered
LAB, or from an odd-numbered LAB to another odd-numbered LAB. For
example, the last LE of the first LAB in a row cascades to the second LE of
the third LAB. The cascade chain does not cross the center of the row. For
example, in an EPF6016 device, the cascade chain stops at the 11th LAB in
a row and a new cascade chain begins at the 12th LAB.
Figure 6 shows how the cascade function can connect adjacent LEs to form
functions with a wide fan-in. In this example, functions of 4n variables are
implemented with n LEs. The cascade chain requires 3.4 ns to decode a
16-bit address.
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