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A1010B-xxxx Schematic ( PDF Datasheet ) - Actel Corporation

Teilenummer A1010B-xxxx
Beschreibung (A1010B / A1020B) FPGAs
Hersteller Actel Corporation
Logo Actel Corporation Logo 




Gesamt 24 Seiten
A1010B-xxxx Datasheet, Funktion
www.DataSheet4U.com
ACT1 Series FPGAs
Features
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL® Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
Description
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE® antifuse technology. The unique architecture offers
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
mclock driver with a hardwired distribution network. The
.conetwork provides efficient clock distribution with minimum
skew.
t4UThe user-definable I/Os are capable of driving at both TTL
eand CMOS drive levels. Available packages include plastic
eand ceramic J-leaded chip carriers, ceramic and plastic quad
hflatpacks, and ceramic pin grid array.
w.DataSApril 1996
ww © 1996 Actel Corporation
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Product Family Profile
Device
A1010B A1020B
A10V10B A10V20B
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
1,200
3,000
30
12
2,000
6,000
50
20
Logic Modules
295 547
Flip-Flops (maximum)
147 273
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
22
13
112,000
22
13
186,000
User I/Os (maximum)
57 69
Packages:
44 PLCC 44 PLCC
68 PLCC 68 PLCC
84 PLCC
100 PQFP 100 PQFP
80 VQFP 80 VQFP
84 CPGA 84 CPGA
84 CQFP
Performance
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
75 MHz
55 MHz
75 MHz
55 MHz
Note: See Product Plan on page 1-286 for package availability.
The Designer and Designer
Advantage™ Systems
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft® Windowsand X Windowsgraphical user
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmapVHDL optimization and synthesis tool
and the ACTgenMacro Builder, a powerful macro function
generator for counters, adders, and other structural blocks.
1-283






A1010B-xxxx Datasheet, Funktion
www.DataSheet4U.com
Electrical Specifications (5V)
Commercial
Industrial
Military
Symbol
Parameter
Min.
Max.
Min.
VOH1
(IOH = –10 mA)2
(IOH = –6 mA)
VOL1
(IOH = –4 mA)
(IOL = 10 mA)2
(IOL = 6 mA)
VIL
VIH
Input Transition Time tR, tF2
CIO I/O Capacitance2, 3
Standby Current, ICC4 (typical = 1 mA)
Leakage Current5
2.4
3.84
–0.3
2.0
–10
0.5
0.33
0.8
VCC + 0.3
500
10
3
10
3.7
–0.3
2.0
–10
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz.
4. Typical standby current = 1 mA. All outputs unloaded. All inputs = VCC or GND.
5. VO , VIN = VCC or GND.
Max.
0.40
0.8
VCC + 0.3
500
10
10
10
Min.
3.7
–0.3
2.0
–10
Max. Units
0.40
0.8
VCC + 0.3
500
10
20
10
V
V
V
V
V
V
V
ns
pF
mA
µA
Electrical Specifications (3.3V)
Parameter
Commercial
Min. Max.
VOH1
VOL1
(IOH = –4 mA)
(IOH = –3.2 mA)
(IOL = 6 mA)
VIL
VIH
Input Transition Time tR, tF2
CIO I/O Capacitance2, 3
Standby Current, ICC4 (typical = 0.3 mA)
Leakage Current5
2.15
2.4
–0.3
2.0
–10
0.4
0.8
VCC + 0.3
500
10
0.75
10
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
m3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz.
o4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND.
.c5. VO, VIN = VCC or GND
www.DataSheet4U1-288
Units
V
V
V
V
V
ns
pF
mA
µA

6 Page









A1010B-xxxx pdf, datenblatt
www.DataSheet4U.com
Temperature and Voltage Derating
Factors (normalized to Worst-Case
Commercial, TJ = 3.0 V, 70°C)
0 25 70
2.7 1.05 1.09 1.30
3.0 0.81 0.84 1.00
3.3 0.64 0.67 0.79
3.6 0.62 0.64 0.76
Junction Temperature and Voltage Derating Curves
(normalized to Worst-Case Commercial, TJ = 3.0 V, 70°C)
1.3
1.2
1.1
1.0
0.9
0.8
70°C
0.7
25°C
0.6 0°C
0.5
2.7
3.0 3.3
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
3.6
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