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PDF AL260 Data sheet ( Hoja de datos )

Número de pieza AL260
Descripción Video Enhancement Processor
Fabricantes Averlogic Technologies 
Logotipo Averlogic Technologies Logotipo



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Video Enhancement
Processor
AL260 Data Sheets
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AL260 pdf
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AL260
1. General Description
AL260 is a highly integration Video Enhancement Processor which supports video input
with multiple video formats then output with De-interlacing and Scaling effects. It can be
used for most video conversion and processing applications.
AL260 is equipped with a high quality scaling engine that automatically maintains full
screen output display, regardless of the resolution of the incoming signals. Applying
AverLogic’s proprietary scaling algorithm, the primary input video can be scaled up and
scaled down independently in horizontal & vertical directions. It also provides film
detection, advanced de-interlacing, filtering, and scaling which’s able to convert and
process the interlaced video to be displayed on progressive panels.
The On Screen Display (OSD) window provides overlay of a control menu, text, or caption
on the output display. It’s built-in OSD generator with 2K Bytes programmable RAM fonts
and also supports optional external OSD.
AL260 is built-in 3-channel DAC for non-interlaced analog output and also supports 24bit
digital output. It’s housed with 208-pin QFP.
www©2.D00a2t,a20S0h3e-Ceot4pyUri.gchotmby AverLogic Technologies, Corp.
Version B1.0
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AL260 arduino
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7 Pin Definition and Description
7.1Input Format Table of AL260:
VIN No.
VIDEO
15~8
Y
7~0
CbCr
YCbCr
AL260
The pin-out definitions are described as follows:
Pin Name
Pin Number
Input Interface
VIN
[15:14],
49-48,
[13:10],
46-43,
[9:8]
41-40
VIN
[7:4],
33-30,
[3:0]
28-25
VCLK
35
VHREFF
37
VHS
38
VVS
39
OSD ROM Interface
RDATA
[6:0],
22-16,
[7] 24
RA
[15:0]
203-188
DAC Output Interface
AVDD33
154
AVSS33
136
AVDD25
152
AVSS25
153
AVDD33R
146
I/O type
Description
I Video Input Bus Bit 15-8, lower 8 bits of ITU-R 601
16bit data bus
I Video Input Bus Bit 7-0, upper 8 bits of ITU-R 601
16bit data bus OR
Video Input Bus Bit 7-0 of ITU-R 656 8bit
I Reference Clock of Video Port
I HDE of Video Port
I HSYNC of Video Port
I VSYNC of Video Port
I ROM Data Bus Bit 7-0
O ROM Address Bus Bit 15-0
AP 3.3v Analog Power for DAC
AG Analog GND for DAC
AP 2.5V Analog Power for DAC
AG Analog GND for DAC
AP 3.3 V Analog Power for Channel R
ww©w2.0D02a,t2a0S03h-eCeotp4yUrig.chtobmy AverLogic Technologies, Corp.
Version B1.0
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