Datenblatt-pdf.com


3TN144L4W Schematic ( PDF Datasheet ) - Lattice Semiconductor

Teilenummer 3TN144L4W
Beschreibung (3TN1xxC) MachXO Family
Hersteller Lattice Semiconductor
Logo Lattice Semiconductor Logo 




Gesamt 30 Seiten
3TN144L4W Datasheet, Funktion
www.DataSheet4U.com
MachXO Family Data Sheet
Version 02.1_4W May 2006
www.DataSheet4U.com






3TN144L4W Datasheet, Funktion
www.DataSheet4U.com
Lattice Semiconductor
Figure 2-3. Top View of the MachXO256 Device
JTAG Port
Architecture
MachXO Family Data Sheet
Programmable Function
Units without RAM (PFFs)
PIOs Arranged
into sysIO Banks
Programmable
Function
Units with
RAM (PFUs)
PFU Blocks
The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will
use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs
and 25 outputs associated with each PFU block.
Figure 2-4. PFU Diagram
From
Routing
FCIN
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
LUT4 &
CARRY
LUT4 &
CARRY
Slice 2
LUT4 &
CARRY
LUT4 &
CARRY
FCO
Slice 3
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
Slice
Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice.
The registers in the Slice can be configured for positive/negative and edge/level clocks.
www.DataSheet4U.com
2-3

6 Page









3TN144L4W pdf, datenblatt
www.DataSheet4U.com
Lattice Semiconductor
Architecture
MachXO Family Data Sheet
sysCLOCK Phase Locked Loops (PLLs)
The MachXO1200 and MachXO2280 provide PLL support. The source of the PLL input divider can come from an
external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from
CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from
the routing (or from an external pin). There is a PLL_LOCK signal to indicate that the PLL has locked on to the input
clock signal. Figure 2-10 shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-10. PLL Diagram
Dynamic Delay Adjustment
LOCK
RST
CLKI
(from routing or
external pin)
Input Clock
Divider
(CLKI)
Delay
Adjust
Voltage
ConVtCroOlled
Oscillator
Post Scalar
Divider
(CLKOP)
CLKFB
(from Post Scalar
Divider output,
clock net,
routing/external
pin or CLKINTFB
port
Feedback
Divider
(CLKFB)
Phase/Duty
Select
CLKOS
Secondary
Clock
Divider
(CLKOK)
CLKOP
CLKOK
CLKINTFB
(internal feedback)
Figure 2-11 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-11. PLL Primitive
RST
CLKI
CLKFB
DDA MODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
www.DataSheet4U.com
EHXPLLC
CLKOP
CLKOS
CLKOK
LOCK
CLKINTFB
2-9

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 3TN144L4W Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
3TN144L4W(3TN1xxC) MachXO FamilyLattice Semiconductor
Lattice Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche