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Teilenummer | CDB44600 |
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Beschreibung | 6-Channel Digital Amplifier Controller | |
Hersteller | Cirrus Logic | |
Logo | ||
Gesamt 30 Seiten www.DataSheet4U.com
CS44600
6-Channel Digital Amplifier Controller
Features
> 100 dB Dynamic Range - System Level
< 0.03% THD+N @ 1 W - System Level
32 kHz to 192 kHz Sample Rates
Internal Oscillator Circuit Supports 24.576 MHz
to 54 MHz Crystals
Integrated Sample Rate Converter (SRC)
– Eliminates Clock Jitter Effects
– Input Sample Rate Independent Operation
Power Supply Rejection Realtime Feedback
Spread Spectrum Modulation - Reduces
Modulation Energy
PWM PopGuard® for Single-Ended Mode
Eliminates AM Frequency Interference
Programmable Load Compensation Filters
Support for up to 40 kHz Audio Bandwidth
Digital Volume Control with Soft Ramp
– +24 to -127 dB in 0.25 dB Steps
Per Channel Programmable Peak Detect and
Limiter
SPI and I²C Host Control Interfaces
Separate 2.5 V to 5.0 V Serial Port and Host
Control Port Supplies
PS_SYNC
XTI
XTO
SYS_CLK
DAI_MCLK
DAI_SCLK
DAI_LRCK
DAI_SDIN1
DAI_SDIN2
DAI_SDIN3
MUTE
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
RST
INT
PWM
Clock
Control
Auto Fs
Detect
DAI
Serial
Port
SRC
Volume
/ Limiter
Volume
/ Limiter
Volume
/ Limiter
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Multibit
Σ∆
Modulator
Power
Supply
Rejection
PWM
Conversion
PWM
Conversion
PWM
Conversion
PSR_RESET
PSR_EN
PSR_MCLK
PSR_SYNC
PSR_DATA
PWMOUTA1+
PWMOUTA1-
PWMOUTB1+
PWMOUTB1-
PWMOUTA2+
PWMOUTA2-
PWMOUTB2+
PWMOUTB2-
PWMOUTA3+
PWMOUTA3-
PWMOUTB3+
PWMOUTB3-
SPI/I2C Host
Control Port
PWM
Backend
Control/
Status
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
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Preliminary Product Information This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
MAY '05
DS633PP1
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CS44600
LIST OF FIGURES
Figure 1. Performance Characteristics Evaluation Active Filter Circuit......................................... 10
Figure 2. XTI Timings.................................................................................................................... 11
Figure 3. SYS_CLK Timings ......................................................................................................... 12
Figure 4. PWMOUTxx Timings ..................................................................................................... 12
Figure 5. PS_SYNC Timings......................................................................................................... 12
Figure 6. Serial Audio Interface Timing......................................................................................... 13
Figure 7. Serial Audio Interface Timing - TDM Mode.................................................................... 13
Figure 8. Control Port Timing - I²C Format.................................................................................... 14
Figure 9. Control Port Timing - SPI Format................................................................................... 15
Figure 10. CS44600 Pinout Diagram ............................................................................................ 16
Figure 11. Typical Full-Bridge Connection Diagram ..................................................................... 20
Figure 12. Typical Half-Bridge Connection Diagram..................................................................... 21
Figure 13. CS44600 Data Flow Diagram (Single Channel Shown) .............................................. 23
Figure 14. Fundamental Mode Crystal Configuration ................................................................... 24
Figure 15. 3rd Overtone Crystal Configuration ............................................................................. 25
Figure 16. CS44600 Internal Clock Generation ............................................................................ 25
Figure 17. I²S Serial Audio Formats.............................................................................................. 27
Figure 18. Left-Justified Serial Audio Formats .............................................................................. 27
Figure 19. Right-Justified Serial Audio Formats............................................................................ 28
Figure 20. One Line Mode #1 Serial Audio Format....................................................................... 28
Figure 21. One Line Mode #2 Serial Audio Format....................................................................... 29
Figure 22. TDM Mode Serial Audio Format .................................................................................. 29
Figure 23. De-Emphasis Curve..................................................................................................... 30
Figure 24. Control Port Timing in SPI Mode ................................................................................. 35
Figure 25. Control Port Timing, I²C Slave Mode Write.................................................................. 36
Figure 26. Control Port Timing, I²C Slave Mode Read.................................................................. 36
Figure 27. Recommended CS44600 Power Supply Decoupling Layout....................................... 38
Figure 28. Recommended CS44600 Crystal Circuit Layout ......................................................... 39
Figure 29. Recommended PSR Circuit Layout ............................................................................. 40
Figure 30. PSR Calibration Sequence .......................................................................................... 43
Figure 31. PWM Output Delay ...................................................................................................... 69
Figure 32. 64-Pin LQFP Package Drawing ................................................................................... 75
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DS633PP1
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SWITCHING CHARACTERISTICS - SYS_CLK
(VD = 2.5 V, VDP = VLC = VDX = 3.3 V, VLS = 2.5 V to 5.0 V, Cload = 50 pF)
Parameter
SYS_CLK Period
SYS_CLK Duty Cycle
Symbol
tsclki
Min
18.518
45
Typ
---
50
SYS_CLK
tsclki
Figure 3. SYS_CLK Timings
CS44600
Max
Unit
--- ns
55 %
SWITCHING CHARACTERISTICS - PWMOUTA1-B3
(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V unless otherwise specified, Cload = 10 pF)
Parameter
Symbol
Min
Typ
Max
Unit
PWMOUTxx Period
Rise Time of PWMOUTxx
tpwm
2.60
-
1.18 µs
VDP = 5.0 V tr - 1.6 - ns
VDP = 3.3 V
- 2.1 - ns
Fall Time of PWMOUTxx
VDP = 5.0 V tf - 1.1 - ns
VDP = 3.3 V
- 1.4 - ns
PWMOUTxx
tr
tf
tpwm
Figure 4. PWMOUTxx Timings
SWITCHING CHARACTERISTICS - PS_SYNC
(VD = 2.5 V, VLS = VLC = VDX = 3.3 V, VDP = 3.3 V to 5.0 V, Cload = 20 pF)
Parameter
PS_SYNC Period
PS_SYNC Duty Cycle
Symbol
tpsclki
Min
592.576
45
Typ
---
50
PS_SYNC
Max
Unit
--- ns
55 %
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tpsclki
Figure 5. PS_SYNC Timings
12 DS633PP1
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ CDB44600 Schematic.PDF ] |
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