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DM9102A Schematic ( PDF Datasheet ) - DAVICOM

Teilenummer DM9102A
Beschreibung Single Chip Fast Ethernet NIC controller
Hersteller DAVICOM
Logo DAVICOM Logo 




Gesamt 30 Seiten
DM9102A Datasheet, Funktion
www.DataSheet4U.com
General Description
The DM9102A is a fully integrated and cost-effective single
chip Fast Ethernet NIC controller. It is designed with the low
power and high performance process. It is a 3.3V device
with 5V tolerance then it supports 3.3V and 5V signaling.
The DM9102A provides direct interface to the PCI or the
CardBus. It supports bus master capability and fully
complies with PCI 2.2. In media side, The DM9102A
interfaces to the UTP3,4,5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliance with the IEEE 802.3u
DM9102A
Single Chip Fast Ethernet NIC controller
Spec. Its auto-negotiation function will automatically
configure the DM9102A to take the maximum advantage of
its abilities. The DM9102A is also support IEEE 802.3x full-
duplex flow control.
The DM9102A supports two types of power-management
mechanisms. The main mechanism is based upon the
OnNow architecture, which is required for PC99. The
alternative mechanism is based upon the remote Wake-On-
LAN mechanism.
Block Diagram
TX+/-
RX+/-
EEPROM
Interface
Boot ROM /
MII Interface
DMA
NRZI to MLT3
PHYceiver
NRZ to NRZI
Parallel to
Serial
Scrambler
4B/5B
Encoding
AEQ MLT3 to NRZI
NRZI to NRZ
Parallel to
Serial
De-
Scrambler
4B/5B
Decoding
MAC
TX
Machine
TX
FIFO
MII
RX
Machine
RX
FIFO
PCI
Interface
LED Driver
Autonegotiation
MII Management Control
& MII Register
Power
Management
Block
PME#
WOL
Finwal ww.DataSheet4U.com
Version: DM9102A-DS-F03
August 28, 2000
1






DM9102A Datasheet, Funktion
www.DataSheet4U.com
Pin Configuration : 128 pin TQFP
DM9102A
Single Chip Fast Ethernet NIC controller
X2
X1/OSC
DGND
SUBGND
BGRESG
BGRES
AVDD
AVDD
RXI+
RXI-
AGND
AGND
TXO+
TXO-
AVDD
AVDD
INT#
PCICLK
ISOLATE#
GNT#
REQ#
DVDD
AD31
AD30
AD29
AD28
DGND
AD27
AD26
AD25
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DM9102A
6 www.DataSheet4U.com
64 BPAD2 (MD2)
63 BPAD1 (MD1)
62 BPAD0 (MD0/EEDI)
61 DVDD
60 AD0
59 AD1
58 DGND
57 AD2
56 AD3
55 AD4
54 AD5
53 DVDD
52 DVDD
51 AD6
50 AD7
49 AD8
48 CBE0#
47 AD9
46 DGND
45 DGND
44 AD10
43 AD11
42 DVDD
41 AD12
40 AD13
39 AD14
38 AD15
37 DGND
36 CLOCKRUN#
35 DGND
34 CBE1#
33 PAR
Final
Version: DM9102A-DS-F03
August 28, 2000

6 Page









DM9102A pdf, datenblatt
www.DataSheet4U.com
90
Network Interface
Pin No.
128QFP/128TQFP
105,106
109,110
SPEED10#
/ LINK#
DM9102A
Single Chip Fast Ethernet NIC controller
O LED output pin, active low
mode 0 = 10Mbps LED
mode 1 = Link LED
Pin Name
RXI+
RX-
TXO+
TXO-
I/O Description
I 100M/10Mbps differential input pair.
These two pins are differential receive input pair for
100BASE-TX and 10BASE-T. They are capable of receiving
100BASE-TX MLT-3 or 10BASE-T Manchester encoded
data.
O 100M/10Mbps differential output pair.
These two pins are differential output pair for 100BASE-TX
and 10BASE-T. This output pair provides controlled rise and
fall times designed to filter the transmitter output.
Miscellaneous Pins
Pin No.
128QFP/128TQFP
36
Pin Name
CLOCKRUN#
71 TEST2
75 TEST1
95 WOL/CSTSCHG
97 X2
98 X1/OSC
102 BGRES
12www.DataSheet4U.com
I/O Description
I/O, Clockrun#
O/D The clockrun# signal is used by the system to pause or slow
down the PCI clock signal. It is used by the DM9102A to
enable or disable suspension of the PCI clock signal or restart
of the PCI clock. When the clockrun# signal is not used, this pin
should connected to an external pull-down resistor.
I TEST mode control 2
In normal operation, this pin is pulled-high.
I TEST mode control 1
In normal operation, this pin is pulled low.
O Wake up signal/Card Status Change
This is multiplexed pin to provide Wake on LANsignal or Card
Status Change. In a PCI system, it is used as a WOL signal. In
a CardBus system, it is used as the Card Status Change
output signal and is asynchronous to the clock signal. It
indicates that a power management event has occurred in a
CardBus system. The DM9102A can assert this pin if it detects
link status change, or magic packet, or sample frame. The
default is “normal low, active high pulse”. DM9102A also
support High/Low and Pulse/Level options.
O Crystal feedback output pin used for crystal connection only.
²Leave this pin open if oscillator is used.
I Crystal or Oscillator input. (25MHZ 50ppm)
25MHz Oscillator or series-resonance, fundamental
frequency crystal.
I Bandgap Voltage Reference Resistor.
Final
Version: DM9102A-DS-F03
August 28, 2000

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