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PDF AN178 Data sheet ( Hoja de datos )
| Número de pieza | AN178 | |
| Descripción | Modeling the PLL | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DataSheet4U.com
AN178
Modeling the PLL
DataShee
1988 Dec
DataSheet4U.com
Philips
Semiconductors
DataSheet4 U .com
DataSheet4U.com
1 page  
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Philips Semiconductors
Modeling the PLL
Application note
AN178
FUNCTION
GENERATOR
fI
PLL
UNDER
TEST
1BIAS
) VCC
BIAS AND
GAIN SET
KHRON–NITE
FILTER #1
FREE–RUNNING
FREQUENCY SET
VCO
OUT
fο
LOW PASS
FILTER
DVM
VD
GAIN–PHASE
METER
θο
KHRON–NITE
FILTER #2
OSCILLOSCOPE
FREQUENCY
COUNTER
fIfo
Figure 5. Measurement Scheme for Kd and Ko Determinations
SL01015
et4U.com
The procedure to follow for obtaining Kd and Ko is as follows:
Kd is generally constant over wide frequency ranges, but is linearily
1. Establish the desired external bias and gain conditions for the
PLL under test.
related to the input signal amplitude. Ko is constant with input signal
level but does vary linearily with fO’. Often it is convenient to specify
a normalized Ko as
2. With the Function Generator turned off, set the free-running
frequency of the loop via the timing capacitor and timing
if appropriate. Monitor fO’ with the Frequency Counter.
reDsaisttaorSheet4U.cKoOm(norm)
+
KO rad
fOȀ V
(15)
3. Turn on the Function Generator and check to make sure the
amplitude of the input signal is appropriate for the particular loop
under test.
4. Adjust the input frequency for lock. Lock is discernable on a
dual-trace scope when the input and VCO waveforms are
synchronized and stationary with respect to each other. One
should be especially careful to check that locking has not
occurred between the VCO and some harmonic frequency.
Carefully inspect both waveshapes, making sure each has the
same period. (If a second Frequency Counter is available, an
alternate scheme can be used to confirm frequency locking.
One frequency counter is used to monitor the input signal
frequency, and the second counter is used for the VCO
frequency. When the two counters display the same frequency,
the PLL is locked.)
5. Set the input frequency to the free-running frequency and note
the Gain-Phase Meter display. It should be approximately 90°
±10° nominally. Record the phase error, θe, the VCO control
voltage, VD, and the input frequency, fl.
6. Adjust fl for frequencies above and below fO’ and record θe and
VD for each fl, as appropriate.
The Ko value at any desired free-running frequency then can be
estimated as
KO (@ any%fOȀ ) + Ko(norm)fOȀ
(16)
AThe loop gain for the PLL system is
Kv + KdKoA
(17)
(Often when the gain A is due to an amplifier internal to the IC, A will
be included in either Kd or Ko. This is further illustrated in the article
on the 565 PLL.)
MODELING THE PLL SYSTEM WITH VARIOUS
LOW-PASS FILTERS
The open-loop transfer function for the PLL is
T(s)
+
KVF(s)
s
(18)
Using linear feedback analysis techniques, and assuming that the
VCO is in the forward path, the closed-loop transfer characteristics
H(s) can be related to the open-loop performance as
7. Making a plot of VD versus θe is useful for checking the
measurement data and the system’s linearity. The slope of this
plot (∆VD/∆θe) is Kd in units of V/°. Multiplying this slope by
180/π gives the desired Kd in volts/radian.
8. A plot of fl = fO versus VD while the loop remains locked will
check the VCO linearity. The slope of this plot is Ko at the
particular free-running frequency. The units of slope taken
directly from the graph are Hz/V. Multiplying this slope figure by
DataSheet4U.2cπomgives the desired Ko in units of radians/ volt-sec.
H(s)
+
1
T(s)
) T(s)
(19)
and the roots of the characteristic system polynomial can be readily
determined by root-locus techniques.
From these equations, it is apparent that the transient performance
and frequency response of the loop is heavily dependent upon the
choice of filter and its corresponding transfer characteristic, F(s).
DataShee
1988 Dec
DataSheet4 U .com
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Philips Semiconductors
Modeling the PLL
Application note
AN178
Thus, for a given DC phase comparator output VE, an input
amplitude decrease must be accompanied by a phase change.
Since the loop can remain locked only for θi between 0 and 180°,
the lower Vl becomes, the more the lock range is reduced.
Note from the second term that during lock the lowest possible
frequency is ωO + ωI = 2ωI. A sum frequency component is always
present at the phase comparator output. This component is usually
Quadrature-Phase Detector (QPD)
The quadrature-phase detector action is exactly the same except
that its output is proportional to the sine of the phase angle. When
the phase θi is 90°, the quadraturephase detector output is then at
its maximum, which explains why it makes a useful lock or
amplitude detector. The output of the quadrature-phase detector is
given by
greatly attenuated by the low-pass filter capacitor connected to the
phase comparator output. However, when rapid tracking is required
(as with high-speed FM detection or FSK), the requirement for a
relatively high frequency cutoff in the low-pass filter may leave this
component unattenuated to the extent that it interferes with
Vq
+
2AqVI
p
sin
qi
(64)
where Vl is the constant or modulated AM signal and θi ≈ 90° in
most cases so that sine θi = 1 and
detection. At the very least, additional filtering may be required to
remove this component. Components caused by n ≠ 0 in the
Vq
+
2AqVI
p
(65)
second term are both attenuated and of much higher frequency, so
they may be neglected.
This is the demodulation principle of the autodyne receiver and the
basis for the 567 tone decoder operation.
Suppose that other frequencies represented by Vk are present.
What is their effect for Vk ≠ 0?
et4U.com
The third term shows that Vk introduces another difference
frequency component. Obviously, if ωk is close to ωI, it can interfere
with the locking process since it may form a beat frequency of the
same magnitude as the desired locking beat frequency. However,
suppose lock has been achieved so that ωO = ωI. In order for lock
to be maintained, the average phase comparator output must be
constant. If ωO = ωk is relatively low in frequency, the phase θi must
change to compensate for this beat frequency. Broadly speaking,
INITIAL PLL SETUP CHOICES
In a given application, maximum PLL effectiveness can be achieved
if the designer understands the tradeoffs which can be made.
Generally speaking, the designer is free to select the frequency, lock
range, capture range, and input amplitude.
FREE-RUNNING FREOUENCY SELECTION
any signal in addition to the signal to which the loop is locked
Setting the center or free-running frequency is accomplished by
causes a phase variation. Usually this is negligible since ωk iDs aofttaenSheet4sUel.eccotimng one or two external components. The center frequency is
far removed from ωI. However, it has been stated that the phase θi
usually set in the center of the expected input frequency range.
can move only between 0 and 180°. Suppose the phase limit has
Since the loop’s ability to capture is a function of the difference
been reached and Vk appears. Since it cannot be compensated for,
it will drive the loop out of lock. This explains why extraneous
between the incoming and free-running frequencies, the band edges
of the capture range are always an equal distance (in Hz) from the
signals can result in a decrease in the lock range. If Vk is assumed
to be an instantaneous noise component, the same effect occurs.
center frequency. Typically, the lock range is also centered about
the free-running frequency. Occasionally, the center frequency is
When the full swing of the loop is being utilized, noise will decrease
chosen to be offset from the incoming frequency so that the tracking
the lock or tracking range. This effect can be reduced by decreasing
range is limited on one side. This permits rejection of an adjacent
the cutoff frequency of the lowpass filter so that the ωO – ωk is
attenuated to a greater extent, which illustrates that noise immunity
higher or lower frequency signal without paying the penalty for
narrow-band operation (reduced tracking speed).
and out-band frequency rejection is improved (at the expense of
capture range since ωO – ωI is likewise attenuated when the
low-pass filter capacitor is large.
All of Philips Semiconductors loops use a phase comparator in
which the input signal is multiplied by a unity square wave at the
VCO frequency. The odd harmonics present in the square wave
The third term can have a DC component when ωk is an odd
harmonic of the locked frequency so that (2n + 1) (ωO – ωI) is zero
and θk makes its appearance. This will have an effect on θ1 which
will change the θ1 versus frequency ωI. This is most noticeable
when the waveform of the incoming signal is, for example, a square
wave. The θk term will combine with the θ1 term so that the phase is
a linear function of input frequency. Other waveforms will give
different phase versus frequency functions. When the input
permit the loop to lock to input signals at these odd harmonics.
Thus, the center frequency may be set to, say, 1/3 or 1/5 of the input
signal. The tracking range, however, will be considerably reduced
as the higher harmonics are utilized.
The foregoing phase comparator discussion would suggest that the
PLL cannot lock to subharmonics because the phase comparator
cannot produce a DC component if ωI is less than ωO.
amplitude Vl is large and the loop gain is large, the phase will be
close to 90° throughout the range of VCO swing, so this effect is
The loop can lock to both odd harmonic and subharmonic signals in
practice because such signals often contain harmonic components
often unnoticed.
The fourth term is of little consequence except that if ωk approaches
zero, the phase comparator output will have a component at the
locked frequency ωO at the output. For example, a DC offset at the
input differential stage will appear as a square wave of fundamental
ωO at the phase comparator output. This is usually small and well
attenuated by the low-pass filter. Since many out-band signals or
noise components may be present, many Vk terms may be
DataSheet4cUom.cboinming to influence locking and phase during lock. Fortunately,
only those close to the locked frequency need be considered.
at ωO. For example, a square wave of fundamental ωO/3 will have a
substantial component at ωO to which the loop can lock. Even a
pure sine wave input signal can be used for harmonic locking if the
PLL input stage is overdriven. (The resultant internal limiting
generates harmonic frequencies.) Locking to even harmonics or
subharmonics is the least satisfactory, since the input or VCO signal
must contain second harmonic distortion. If locking to even
harmonics is desired, the duty cycle of the input and VCO signals
must be shifted away from the symmetrical to generate substantial,
even harmonic, content.
DataShee
1988 Dec
DataSheet4 U .com
11 DataSheet4U.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AN178.PDF ] | |
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