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39SF51270 Schematic ( PDF Datasheet ) - Silicon Storage Technology

Teilenummer 39SF51270
Beschreibung SST39SF512-70
Hersteller Silicon Storage Technology
Logo Silicon Storage Technology Logo 




Gesamt 22 Seiten
39SF51270 Datasheet, Funktion
www.DataSheet4U.com
www.DataSheet4U.com
512 Kbit / 1 Mbit (x8) Multi-Purpose Flash
SST39SF512 / SST39SF010
FEATURES:
SST39SF512 / 0105.0V 512Kb / 1Mb (x8) MPF memories
Data Sheet
• Organized as 64K x8 / 128K x8
• Single 5.0V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 20 mA (typical)
Standby Current: 10 µA (typical)
Sector-Erase Capability
Uniform 4 KByte sectors
Fast Read Access Time:
70 ns
90 ns
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 7 ms (typical)
Chip-Erase Time: 15 ms (typical)
Byte-Program Time: 20 µs (typical)
Chip Rewrite Time:
2 seconds (typical) for SST39SF512
3 seconds (typical) for SST39SF010
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
TTL I/O Compatibility
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-pin PLCC
32-pin TSOP (8mm x 14mm)
32-pin PDIP
PRODUCT DESCRIPTION
The SST39SF512/010 are CMOS Multi-Purpose Flash
(MPF) manufactured with SSTs proprietary, high perfor-
mance CMOS SuperFlash technology. The split-gate cell
design and thick oxide tunneling injector attain better reli-
ability and manufacturability compared with alternate
approaches. The SST39SF512/010 devices write (Pro-
gram or Erase) with a 5.0V-only power supply. The
SST39SF512/010 device conforms to JEDEC standard
pinouts for x8 memories.
Featuring high performance Byte-Program, the
SST39SF512/010 devices provide a maximum Byte-Pro-
gram time of 30 µsec. These devices use Toggle Bit or
Data# Polling to indicate the completion of Program opera-
tion. To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39SF512/010 devices are suited for applications
that require convenient and economical updating of pro-
gram, configuration, or data memory. For all system appli-
cations, they significantly improve performance and
rweliawbwility.,DwahtilaeSlohweereintg4pUo.wceor mconsumption. They inher-
ently use less energy during erase and program than alter-
native flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of applica-
tion. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter
erase time, the total energy consumed during any Erase or
Program operation is less than alternative flash technolo-
gies. These devices also improve flexibility while lowering
the cost for program, data, and configuration storage appli-
cations.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST39SF512/010 are offered in 32-pin PLCC packages,
32-pin TSOP, and a 600 mil, 32-pin PDIP is also available.
See Figures 1, 2, and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
©2001 Silicon Storage Technology, Inc.
S71149-03-000 4/01
394
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.






39SF51270 Datasheet, Funktion
www.DataSheet4U.com
www.DataSheet4U.com
512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
AMS1-A0
Pin Name
Address Inputs
DQ7-DQ0 Data Input/output
CE#
OE#
WE#
VDD
VSS
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Functions
To provide memory addresses.
During Sector-Erase AMS-A12 address lines will select the sector.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide 5.0V supply (±10%)
Unconnected pins.
1. AMS = Most significant address
AMS = A15 for SST39SF512 and A16 for SST39SF010
T2.3 394
TABLE 3: OPERATION MODES SELECTION
Mode
Read
Program
Erase
CE#
VIL
VIL
VIL
OE#
VIL
VIH
VIH
WE#
VIH
VIL
VIL
DQ
DOUT
DIN
X1
Standby
Write Inhibit
Product Identification
Software Mode
VIH X
X High Z
X VIL X High Z/ DOUT
X X VIH High Z/ DOUT
VIL VIL VIH
1. X can be VIL or VIH, but no other value.
Address
AIN
AIN
Sector address,
XXH for Chip-Erase
X
X
X
See Table 4
T3.4 394
www.DataSheet4U.com
©2001 Silicon Storage Technology, Inc.
6
S71149-03-000 4/01 394

6 Page









39SF51270 pdf, datenblatt
www.DataSheet4U.com
www.DataSheet4U.com
512 Kbit / 1 Mbit Multi-Purpose Flash
SST39SF512 / SST39SF010
Data Sheet
ADDRESS AMS-0
CE#
OE#
TOEH
TCE
TOE
WE#
DQ6
Note
Note: Toggle bit output is always high first.
AMS = Most significant address
AMS = A15 for SST39SF512 and A16 for SST39SF010
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
394 ILL F07.1
ADDRESS AMS-0
CE#
5555
SIX-BYTE CODE FOR SECTOR-ERASE
2AAA
5555
5555
2AAA
SAX
TSE
OE#
WE#
TWP
DQ7-0
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 10)
SAX = Sector Address
AMS = Most significant address
www.DataSheet4U.coAMmS = A15 for SST39SF512 and A16 for SST39SF010
FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
394 ILL F08.2
©2001 Silicon Storage Technology, Inc.
12
S71149-03-000 4/01 394

12 Page





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