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P-80C52 Schematic ( Datenblatt PDF ) - Temic

Teilenummer P-80C52
Beschreibung (P-80C32 / P-80C52) CMOS 8-Bit Microcontroller
Hersteller Temic
Logo Temic Logo 

Gesamt 25 Seiten
		
P-80C52 Datasheet, Funktion
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80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller
1. Description
TEMIC’s 80C52 and 80C32 are high performance
CMOS versions of the 8052/8032 NMOS single chip 8
bit Microcontroller.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC,
without loss of data.
The 80C52 retains all the features of the 8052: 8 K bytes
of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit
timers; a 6-source, 2-level interrupt structure; a full
duplex serial port; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2
D 80C32: Romless version of the 80C52
D 80C32/80C52-L16: Low power version
VCC: 2.7 – 5.5 V Freq: 0-16 MHz
D 80C32/80C52-12: 0 to 12 MHz
D 80C32/80C52-16: 0 to 16 MHz
D 80C32/80C52-20: 0 to 20 MHz
D 80C32/80C52-25: 0 to 25 MHz
D 80C32/80C52-30: 0 to 30 MHz
D 80C32/80C52-36: 0 to 36 MHz
software-selectable modes of reduced activity for
further reduction in power consumption. In the idle
mode the CPU is frozen while the RAM, the timers, the
serial port and the interrupt system continue to function.
In the power down mode the RAM is saved and all other
functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are
manufactured using SCMOS process which allows them
to run from 0 up to 44 MHz with VCC = 5 V.
TEMIC’s 80C52 and 80C32 are also available at
16 MHz with 2.7 V < VCC < 5.5 V.
D 80C32-40: 0 to 40 MHz(1)
D 80C32-42: 0 to 42 MHz(1)
D 80C32-44: 0 to 44 MHz(1)
Notes:
1. 0 to 70_C temperature range.
2. For other speed and temperature range availability, please
contact your sales office.
2. Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range: commercial, industrial, automotive,
military
3. Optional
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D Secret ROM: Encryption
D Secret TAG: Identification number
Rev. I September 18, 1998
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P-80C52 Datasheet, Funktion
www.DataSheet4U.com
80C32/80C52
6. Idle And Power Down Operation
Figure 3. shows the internal Idle and Power Down clock configuration. As illustrated, Power Down operation stops
the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the
clock to the CPU is gated off.
These special modes are activated by software via the Special Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
Figure 3. Idle and Power Down Hardware
PCON: Power Control Register
(MSB)
76
SMOD
5
(LSB)
43210
– GF1 GF0 PD IDL
Symbol Position
Name and Function
SMOD
PCON.7
Double Baud rate bit
When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3.
Reserved
– PCON.6
The value read from this bit is indeterminate. Do not set this bit.
Reserved
– PCON.5
The value read from this bit is indeterminate. Do not set this bit.
Reserved
– PCON.4
The value read from this bit is indeterminate. Do not set this bit.
GF1 PCON.3 General–purpose flag bit
GF0 PCON.2 General–purpose flag bit
PD(1)
PCON.1
Power Down bit. Setting this bit activates power down operation
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power–Down mode.
If IDL and PD are both set, PD takes precedence.
Idle mode bit
IDL(1)
PCON.0
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
www.DataSheet4U.comIf IDL and PD are both set, PD takes precedence.
1. If 1’s are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000).
6 Rev. I September 18, 1998

6 Page







P-80C52 pdf, datenblatt
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80C32/80C52
7.2. 80C52 with Secret ROM
TEMIC offers 80C52 with the encrypted secret ROM option to secure the ROM code contained in the 80C52
microcontrollers.
The clear reading of the program contained in the ROM is made impossible due to an encryption through several
random keys implemented during the manufacturing process.
The keys used to do such encryption are selected randomwise and are definitely different from one microcontroller
to another.
This encryption is activated during the following phases :
– Everytime a byte is addressed during a verify of the ROM content, a byte of the encryption array is selected.
– MOVC instructions executed from external program memory are disabled when fetching code bytes from internal
memory.
– EA is sampled and latched on reset, thus all state modification are disabled.
For further information please refer to the application note (ANM053) available upon request.
7.3. 80C52 with Secret TAG
TEMIC offers special 64-bit identifier called “SECRET TAG” on the microcontroller chip.
The Secret Tag option is available on both ROMless and masked microcontrollers.
The Secret Tag feature allows serialization of each microcontroller for identification of a specific equipment. A unique
number per device is implemented in the chip during manufacturing process. The serial number is a 64-bit binary value
which is contained and addressable in the Special Function Registers (SFR) area.
This Secret Tag option can be read-out by a software routine and thus enables the user to do an individual identity check
per device. This routine is implemented inside the microcontroller ROM memory in case of masked version which can
be kept secret (and then the value of the Secret Tag also) by using a ROM Encryption.
For further information, please refer to the application note (ANM031) available upon request.
8. Electrical Characteristics
8.1. Absolute Maximum Ratings(1) in Commercial and Industrial Temp Range
Ambiant Temperature Under Bias:
C = commercial . . . . . . . . . . . . . . . . . . . . . 0_C to 70_C
I = industrial . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 85_C
A = automotive . . . . . . . . . . . . . . . . . . . . . –40_C to +125_C
M = military . . . . . . . . . . . . . . . . . . . . . . . . –55_C to +125_C
Storage Temperature . . . . . . . . . . . . . . . . . –65_C to + 150_C
Voltage on VCC to VSS . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . 1 W(2)
Notes:
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
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