Datenblatt-pdf.com

P-80C32 Schematic ( Datenblatt PDF ) - ETC

Teilenummer P-80C32
Beschreibung P80C32
Hersteller ETC
Logo ETC Logo 

Gesamt 20 Seiten
		
P-80C32 Datasheet, Funktion
www.DataSheet4U.com
80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microntroller
Description
TEMIC’s 80C52 and 80C32 are high performance CMOS
versions of the 8052/8032 NMOS single chip 8 bit µC.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC, without
loss of data.
The 80C52 retains all the features of the 8052 : 8 K bytes
of ROM ; 256 bytes of RAM ; 32 I/O lines ; three 16 bit
timers ; a 6-source, 2-level interrupt structure ; a full
duplex serial port ; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2 software-selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode the
RAM is saved and all other functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are manufactured
using SCMOS process which allows them to run from 0
up to 44 MHz with Vcc = 5 V.
TEMIC’s 80C52 and 80C32 are also available at 16 MHz
with 2.7 V < VCC < 5.5 V.
D 80C32 : Romless version of the 80C52
D 80C32/80C52-L16 : Low power version
Vcc : 2.7 – 5.5 V Freq : 0-16 MHz
D 80C32/80C52-12 : 0 to 12 MHz
D 80C32/80C52-16 : 0 to 16 MHz
D 80C32/80C52-20 : 0 to 20 MHz
D 80C32/80C52-25 : 0 to 25 MHz
D 80C32/80C52-30 : 0 to 30 MHz
D 80C32/80C52-36 : 0 to 36 MHz
D 80C32-40 : 0 to 40 MHz*
D 80C32-42 : 0 to 42 MHz*
D 80C32-44 : 0 to 44 MHz*
* 0 to 70°C temperature range.
For other speed and temperature range availability please consult your
sales office.
Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev. G (14 Jan. 97)
1






P-80C32 Datasheet, Funktion
www.DataSheet4U.com
80C32/80C52
There are three ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware, terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote 1 to PCON.0.
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
Power Down Mode
The instruction that sets PCON.1 is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The hardware reset initiates the Special Fucntion
Register. In the Power Down mode, VCC may be lowered
to minimize circuit power consumption. Care must be
taken to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which freezes the
oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
Table 1 describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the data is a 1, the port
pin is held high during the power down mode by the
strong pullup, T1, shown in Figure 4.
Table 1. Status of the external pins during idle and power down modes.
MODE
Idle
Idle
Power Down
Power Down
PROGRAM MEMORY
Internal
External
Internal
External
ALE
1
1
0
0
PSEN
1
1
0
0
PORT0
Port Data
Floating
Port Data
Floating
PORT1
Port Data
Port Data
Port Data
Port Data
PORT2
Port Data
Address
Port Data
Port Data
PORT3
Port Data
Port Data
Port Data
Port Data
Stop Clock Mode
Due to static design, the TEMIC 80C32/C52 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Figure 4.I/O Buffers in the 80C52 (Ports 1, 2, 3).
I/O Ports
The I/O buffers for Ports 1, 2 and 3 are implemented as
shown in figure 4.
6 MATRA MHS
Rev. G (14 Jan. 97)

6 Page







P-80C32 pdf, datenblatt
www.DataSheet4U.com
80C32/80C52
Absolute Maximum Ratings*
Ambient Temperature Under Bias :
M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to + 150°C
Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7 V
Voltage on Any Pin to VSS . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
* Notice
Stresses at or above those listed under “ Absolute Maximum Ratings”
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
DC Parameters
TA = –55°C + 125°C ; Vss = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
PARAMETER
VIL Input Low Voltage
VIH Input High Voltage (Except XTAL and RST)
VIH1 Input High Voltage (for XTAL and RST)
VOL Output Low Voltage (Port 1, 2 and 3)
VOL1 Output Low Voltage (Port 0, ALE, PSEN)
VOH Output High Voltage (Port 1, 2 and 3)
VOH1 Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
IIL
ILI
ITL
IPD
RRST
CIO
ICC
Logical 0 Input Current (Ports 1, 2 and 3)
Input leakage Current
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
Power Down Current
RST Pulldown Resistor
Capacitance of I/O Buffer
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq 12 MHz Icc op = 1.25 Freq (MHz) + 5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 mA
MIN
MAX UNIT TEST CONDITIONS
– 0.5
0.2 Vcc – 0.1 V
0.2 Vcc + 1.4 Vcc + 0.5 V
0.7 Vcc
Vcc + 0.5 V
0.45 V IOL = 1.6 mA (note 2)
0.45 V IOL = 3.2 mA (note 2)
2.4 V IOH = – 60 µA
Vcc = 5 V ± 10 %
0.75 Vcc
V IOH = – 25 µA
0.9 Vcc
V IOH = – 10 µA
2.4 V IOH = – 400 µA
Vcc = 5 V ± 10 %
0.75 Vcc
V IOH = – 150 µA
0.9 Vcc
V IOH = – 40 µA
– 75 µA Vin = 0.45 V
+/– 10
µA 0.45 < Vin < Vcc
– 750
µA Vin = 2.0 V
75 µA Vcc = 2.0 V to 5.5 V (note 1)
50 200 K
10 pF fc = 1 MHz, Ta = 25_C
Vcc = 5.5 V
1.8 mA
1 mA
10 mA
4 mA
12 MATRA MHS
Rev. G (14 Jan. 97)

12 Page


SeitenGesamt 20 Seiten
PDF Download[ P-80C32.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
P-80C31 P80C31NXP
NXP
P-80C32 P80C32ETC
ETC
P-80C32(P-80C32 / P-80C52) CMOS 8-Bit MicrocontrollerTemic
Temic

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com    |   2019   |  Kontakt  |   Suche