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DPS9245 Schematic ( PDF Datasheet ) - LSI Logic Corporation

Teilenummer DPS9245
Beschreibung High-resolution ADC With Pga Datasheet 11/00
Hersteller LSI Logic Corporation
Logo LSI Logic Corporation Logo 




Gesamt 28 Seiten
DPS9245 Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
DPS9245
High-Resolution ADC
with PGA
Datasheet
The DPS9245 is a versatile, analog front end that combines a high-
resolution 5 megasamples per second (MS/s) 16-bit Analog-to-Digital
Converter (ADC), a built-in reference, and a Programmable Gain
Amplifier (PGA) with resistive input impedance in a 44-pin package.
Figure 1
DPS9245 Block Diagram
RESETB
REFCLK
Differential
Analog In
(INP, INM)
Low-Noise PGA
(7 Settings)
S/H and
ADC
16
OVR_RNG
Data
AD[15:0]
OE
GAIN[2:0]
VREF
The chip includes a digitally-calibrated, pipeline ADC that is calibrated
upon assertion of a simple reset signal. The combination of a low-noise,
high-linearity, high-input impedance buffer (with programmable gain),
wideband S/H, on-board voltage references, and simple digital interface
(16-bit parallel output word synchronous with the master sampling clock),
makes the chip extremely easy to use in a wide variety of systems. The
analog inputs should be driven differentially, and can be AC-coupled or
DC-coupled to a source. Typical applications include high-performance
data acquisition systems, automatic test equipment, and wideband digital
communications receivers present in systems such as wireless
basestations. The performance of the device with respect to linearity and
noise should be considered separately, as indicated by the THD and
SNR specifications provided in this document.
November 2000
Copyright © 1999, 2000 by LSI Logic Corporation. All rights reserved.
www.DataSheet4U.com
1






DPS9245 Datasheet, Funktion
Table 3
Dynamic Linearity Specifications for Sinusoidal Differential Analog Input
Sample
Rate
[MS/s]
Signal
Frequency
[kHz]
PGA
Setting
[dB]
Composite
Signal
Level at
ADC Input
[dBFS]1
HD2
HD3
THD_9
SFDR
5.0 70
0 –0.5 –94 dB max –85 dB max –84 dB max 85 dB min
5.0 70
0 –0.5 –103 dB typ –97 dB typ –92 dB typ 94 dB typ
5.0 70 20 –0.5 –101 dB typ –93 dB typ –90 dB typ 92 dB typ
8.8 60
0 –0.5 –103 dB typ –97 dB typ –92 dB typ 94 dB typ
5.0 900 12 –11.0 –104 dB typ –97 dB typ –94 dB typ 97 dB typ
5.0 900 15 –8.1 –104 dB typ –94 dB typ –91 dB typ 94 dB typ
5.0 900 18 –5.4 –103 dB typ –88 dB typ –88 dB typ 88 dB typ
5.0 900 20 –3.4 –101 dB typ –85 dB typ –84 dB typ 85 dB typ
5.0 900 20 –1.1 –99 dB typ –84 dB typ –82 dB typ 84 dB typ
1. dBFS is dB below full scale signal level, which is 5 V peak-to-peak differential.
Dynamic Linearity Specifications for Two-Tone Differential Analog Input
Table 4 provides the dynamic linearity specifications for two-tone
differential analog input. The following conditions apply:
VDD_ADC = VDDD_ADC = 5.0 V
VDD_ADIO = 3.3 V
REXT = 1.43 k
The following notes apply:
1. The composite signal level relative to full-scale (dBFS) is given at the
ADC input – that is, after the PGA – in order to show the dependence
on PGA gain.
2. 0 dBFS is 5.0V peak-to-peak differential.
6 DPS9245 High-Resolution ADC with PGA

6 Page









DPS9245 pdf, datenblatt
Note that the analog blocks on the chip require significant time to power
on and come up to their quiescent dc states; for example, the voltage
reference power-on time depends on the value of the external reference
decoupling capacitance. Allowance may also be needed for thermal time
constants associated with the package/board.
On power-up, RESETB should be held LOW for at least three cycles of
the clock signal, REFCLK, as shown in Figure 3 below. The power supply
voltages applied to the chip must be stable during this time. REFCLK
must be running for at least three clock cycles prior to the rising edge of
RESETB, and must continue running.
The initialization phase begins on the rising edge of RESETB. No more
than two full REFCLK cycles after the rising edge of RESETB, BUSYB,
an active LOW signal (pin 33), is driven LOW. An internal sequencer
performs the ADC calibration while BUSYB is LOW. When the
initialization is complete, BUSYB is driven HIGH and the chip is ready for
normal operation. The duration of the initialization phase, (the time
BUSYB is LOW) is 150 ms, assuming a 5 MS/s sampling rate.
Notes:
The digital output BUSYB cannot be 3-stated: it is always driven
either HIGH or LOW.
The REFCLK clock must be constantly running throughout the
initialization phase until BUSYB goes HIGH.
Initialization will restart whenever RESETB is cycled; thus, for
initialization to complete correctly, RESETB should not be cycled
while BUSYB is LOW.
Although typically the chip is initialized when power is first applied,
the initialization only occurs when the RESETB is cycled. There is
no “power-on-reset” circuitry on the chip.
12 DPS9245 High-Resolution ADC with PGA

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