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PC74HCT4046A Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PC74HCT4046A
Beschreibung Phase Locked Loop
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PC74HCT4046A Datasheet, Funktion
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 8 — 19 July 2012
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state)
by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent
of S1 to S3.
VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between VCC as
a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features and benefits
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
80 (typical) at VCC VEE = 4.5 V
70 (typical) at VCC VEE = 6.0 V
60 (typical) at VCC VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C






PC74HCT4046A Datasheet, Funktion
NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
[3] For SO16 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
VCC
VI
VSW
Tamb
t/V
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall
rate
see Figure 7
and Figure 8
VCC GND
VCC VEE
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
74HC4053
Min Typ Max
2.0
2.0
GND
VEE
40
-
-
-
-
5.0
5.0
-
-
+25
-
1.67
-
-
10.0
10.0
VCC
VCC
+125
625
139
83
31
74HCT4053
Unit
Min Typ Max
4.5
2.0
GND
VEE
40
-
-
-
-
5.0
5.0
-
-
+25
-
1.67
-
-
5.5
10.0
VCC
VCC
+125
-
139
-
-
V
V
V
V
C
ns/V
ns/V
ns/V
ns/V
10
VCC GND
(V)
8
001aad545
10
VCC GND
(V)
8
001aad546
6 operating area
4
6
operating area
4
22
0
0 2 4 6 8 10
VCC VEE (V)
0
0 2 4 6 8 10
VCC VEE (V)
Fig 7. Guaranteed operating area as a function of the Fig 8. Guaranteed operating area as a function of the
supply voltages for 74HC4053
supply voltages for 74HCT4053
74HC_HCT4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 July 2012
© NXP B.V. 2012. All rights reserved.
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6 Page









PC74HCT4046A pdf, datenblatt
NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Table 8. Static characteristics for 74HCT4053 …continued
Voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at pins nYn or nZ, whichever is assigned as an input.
Vos is the output voltage at pins nZ or nYn, whichever is assigned as an output.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
VIH HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
VIL
LOW-level input
VCC = 4.5 V to 5.5 V
voltage
II
IS(OFF)
input leakage current
OFF-state leakage
current
VI = VCC or GND; VCC = 5.5 V; VEE = 0 V
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
VSW= VCC VEE; see Figure 11
per channel
all channels
IS(ON)
ICC
ON-state leakage
current
supply current
ICC
additional supply
current
Tamb = 40 C to +125 C
VIH HIGH-level input
voltage
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
VSW= VCC VEE; see Figure 12
VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 5.5 V; VEE = 0 V
VCC = 5.0 V; VEE = 5.0 V
per input; VI = VCC 2.1 V; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V
VCC = 4.5 V to 5.5 V
VIL
LOW-level input
VCC = 4.5 V to 5.5 V
voltage
II
IS(OFF)
input leakage current
OFF-state leakage
current
VI = VCC or GND; VCC = 5.5 V; VEE = 0 V
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
VSW= VCC VEE; see Figure 11
per channel
all channels
IS(ON)
ICC
ON-state leakage
current
supply current
ICC
additional supply
current
VCC = 10.0 V; VEE = 0 V; VI = VIH or VIL;
VSW= VCC VEE; see Figure 12
VI = VCC or GND; Vis = VEE or VCC;
Vos = VCC or VEE
VCC = 5.5 V; VEE = 0 V
VCC = 5.0 V; VEE = 5.0 V
per input; VI = VCC 2.1 V; other inputs at VCC
or GND; VCC = 4.5 V to 5.5 V; VEE = 0 V
Min Typ Max
Unit
2.0 -
--
--
-V
0.8 V
1.0 A
- - 1.0 A
- - 1.0 A
- - 1.0 A
- - 80.0 A
- - 160.0 A
- - 225 A
2.0 -
--
--
-V
0.8 V
1.0 A
- - 1.0 A
- - 1.0 A
- - 1.0 A
- - 160.0 A
- - 320.0 A
- - 245 A
74HC_HCT4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 July 2012
© NXP B.V. 2012. All rights reserved.
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