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CLA60000 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer CLA60000
Beschreibung Channel Less CMOS Gate Arrays
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 15 Seiten
CLA60000 Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
CLA60000 Series
Channel less CMOS Gate Arrays
This new family of gate arrays uses many innovative
techniques to achieve 110K gates per chip with
system clock speeds of up to 70MHz. The
combination of high speed, high gate complexity and
low power operation places Zarlink Semiconductor
at the forefront of ASIC capability.
General Description
The CLA60000 gate array family is Zarlink
Semiconductor’s fifth-generation CMOS gate array
product. These arrays allow even higher integration
densities at enhanced system clock rates as need for
many of today’s system applications.
The largest array in the family at 110K gates offers a
tenfold increase in raw gate availability then
channelled gate arrays. In addition, many new
designs features have been incorporated such as
analog functionality, slew rate output control, and
intermediate I/O buffering for optimum data transfer
through peripheral cells.
Also, the low-power characteristics of Zarlink
Semiconductor CMOS processing have been
incorporated in these arrays, easing the thermal
management problems associated with complex
designs of 20,000 gates and above.
Features
• Channel less arrays to 110,000 gates
• 1.4 micron dual layer metal silicon CMOS
process
• Typical Gate Delays of 700ps (NAND2)
• Comprehensive cell library including microcells,
macrocells, and paracells
• Power distribution optimized for maximum noise
immunity
• Slew controlled outputs with up to 24mA drivers
• Fully supported by design software (PDS2) and
popular workstations
• Very high latch up immunity
Figure 1 - CLA60000 Chip Microplot
All CLA60000 arrays have the same construction. A
core of uncommitted transistors is arranged for
optimum connection as logic functions and
surrounded by uncommitted peripheral (I/O) circuitry.
The channel less array architecture is an important
feature - the absence of discrete wiring channels
increases flexibility, reduces track capacitance whilst
significantly increasing transistor sizes for improved
logic performance.
The construction of the basic building blocks have
been planned to support basic logic functions, macro
functions, and core memory functions (RAM and
ROM) with high routability. Logic programmability is
given by dual level metal, with interconnecting vias,
plus a forth level of programmability (contacts).
The overall architecture of these gate arrays has
been designed to exploit many new and emerging
developments in CAD tools. Increasing demands are
now being made for design tools which are faster,
easier to use, and more accurate. The Zarlink
Semiconductor Design System (PDS2) allows full
control over all aspects of design including logic
capture, simulation and layout.
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1
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CLA60000 Datasheet, Funktion
CLA60000 Series
AC Characteristics for Selected Cells
The CLA60000 technology library contains all the
timing information for each cell in the design library.
This information is accessible to the simulator, which
calculates propagation delays for all signal paths in
the circuit design. The PDS2 simulator can
automatically derate timings according to the various
factors such as:
Supply voltage variation (from nominal 5V)
Chip temperature
Processing tolerance
Gate fanout
Input transition time
Input signal polarity
Interconnecting wiring
For initial assessments of feasibility, worst case
estimations of path delays can be done in the
following manner, using the dynamic Characteristics
table as a guide to the normal propagation delays at
25 Deg. C and 5V supply.
For temperatures, Zarlink Semiconductors has
derived a derating multipler (Kt) of +0.3% per
Deg. C
For supply voltage derating, a factor of (Kv) -
25% per volt of VDD Change should be used.
For manufacturing variation (Kp), the tolerance
is ±50%
The maximum variation on typical delays over
the Commercial grade product will be at 4.5V
and 70 Deg. C ambient temperature.
tpd (max)
= Kp x Kv x Kt x tpd (typ)
= 1.50 x (1+(5.0 - 4.5) 0.25) x (1+(70-25) 0.003) x tpd
(typ)
= 1.50 x 1.13 x 1.13 x tpd (typ) = 1.91 x tpd (typ)
The minimum delay, at 5.5V and 0 Deg. C will be:
tpd (min)
= 0.66 x (1-(5.5-5.0) x 0.25) x (1-(25-0)0.003) x tpd
(typ)
= 0.66 x 0.87 x 0.93 x tpd (typ)
= 0.53 x tpd (typ)
A similar calculation may be applied for any voltage
and temperature relevant to the application. An
additional safety factorof ±20% may be applied if
desired for conservative design. For worst case
military grade characteristics, the performance
derating multiplier is 2.57 times the commercial
typical.
Fanout is in gate load units
Name
INTERNAL CORE CELLS
Cells Description
INV2
NAND2
NOR 2
DF
DFRS
1 INVERTER DUAL DRIVE
2 2 - INPUT NAND GATE
2 2 - INPUT NOR GATE
4 MASTER SLAVE
6 MASTER SLAVE D - TYPE
WITH SET AND RESET
Typical Propagation
Delay (nS)
Symbol
Fanout=2
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
0.64
0.39
0.82
0.67
1.11
0.58
1.04
0.93
1.19
1.12
Worst case Propagation Delay (nS)
Commercial
Industrial
Fanout
24
Fanout
24
1.43 1.65 1.50 1.72
0.87 1.05 0.91 1.10
1.83 2.27 1.92 2.38
1.51 2.01 1.58 2.11
2.48 3.24 2.60 3.40
1.30 1.66 1.36 1.74
2.32 2.76 2.44 2.90
2.08 2.44 2.18 2.56
2.66 3.10 2.79 3.25
2.52 3.02 2.65 3.17
Name
IBGATE
IBDF
IBCMOS1
INTERMEDIATE BUFFER CELLS
Cells Description
- LARGE 2 INPUT NAND GATE
+ 2 INPUT NOR
- MASTER SLAVE D-TYPE FLIP FLOP
- CMOS INPUT BUFFER WITH 2
INPUT NAND GATE
Typical Propagation
Delay (nS)
Symbol
Fanout=2
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
0.76
0.50
1.04
0.93
1.11
0.72
Worst case Propagation Delay (nS)
Commercial
Industrial
Fanout
24
Fanout
24
1.69 2.05 1.77 2.15
1.13 1.40 1.19 1.47
2.32 2.76 2.44 2.90
2.08 2.44 2.18 2.56
2.48 2.88 2.60 3.02
1.61 1.83 1.69 1.92
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CLA60000 pdf, datenblatt
CLA60000 Series
OPT12 Large Drive Tri-State Output Buffer
OPT4B
Standard Drive Non-Inverting Tri-State
Output Buffer
OPT10B Large Drive Non-Inverting Tri-State
Output Buffer
OPOD1
Smallest Drive Open-Drain Output
Buffer
OPOD2 Small Drive Open-Drain Output Buffer
OPOD3
Standard Drive Open-Drain Output
Buffer
OPOD6 Medium Drive Open-Drain Output Buffer
OPOD12 Large Drive Open-Drain Output Buffer
OPOD5B Standard Drive Non-Inverting Open
Drain Output Buffer
OPOD11B Large Drive Non-Inverting Open Drain
Output Buffer
OPOS1
OPOS2
OPOS3
OPOS6
OPOS12
Smallest Drive Open-Source Output
Buffer
Small Drive Open-Source Output Buffer
Standard Drive Open-Source Output
Buffer
Medium Drive Open-Source Output
Buffer
Large Drive Open-Source Output Buffer
OPOS5B
OPOS11B
Standard Drive Non-Inverting Open-
Source Output Buffer
Large Drive Non-Inverting Open-Source
Output Buffer
Supply Pads:
OPVP
OPVM
OPVPB
OPVMB
OPVPBB
OPVMBB
VDD Power Pad (Outputs)
GND Power Pad (Outputs)
VDD Power Pad (Outputs):Break in VDD
GND Power Pad (Outputs):Break in
GND
VDD Power Pad (Outputs):Break in VDD
and GND
GND Power Pad (Outputs):Break in
GND and VDD
IBVP
IBVM
IBVPB
IBVMB
IBVPBB
IBVMBB
VDD Power Pad (Buffers)
GND Power Pad (Buffers)
VDD Power Pad (Buffers):Break in VDD
GND Power Pad (Buffers):Break in GND
VDD Power Pad (Buffers):Break in VDD
and GND
GND Power Pad (Buffers):Break in GND
and VDD
LAVP1 Power Pad for Logic Array
LAVP2
LAVP3
LAVP4
LAVP5
LAVM1
LAVM2
LAVM3
LAVM4
LAVM5
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
Power Pad for Logic Array
LAGND
LAVDD
Power Pad for Logic Array
Power Pad for Logic Array
Analogue Cells:
OSC1
Crystal Oscillator Peripheral Cell
ANIPCMP1 Comparator - Standard
ANIPCMP2 Comparator - Low Power
ANADC4 Four Bit Analogue To Digital Converter
ANDAC4 Four Bit Digital To Analogue Converter
ANVREFGN Reference Generator/Power On Reset
ANVREFSH Shunt Regulator/Power On Reset
a) Memory Cells
RAM2
RAM4
RAM8
RAM16
RAM32
RAM64
2 bit memory
4 bit memory
8 bit memory
16 bit memory
32 bit memory
64 bit memory
b) Single port decoder cells
RAD2S
RAD2SL
RAD4S
RAD4SL
RAD8S
RAD8SL
RAD16S
RAD16SL
RAD32S
RAD32SL
RAD64S
RAD64SL
2 words (1-16 bits RAM)
2 words (17-64 bits RAM)
4 words (1-16 bits RAM)
4 words (17-64 bits RAM)
8 words (1-16 bits RAM)
8 words (17-64 bits RAM)
16 words (1-16 bits RAM)
16 words (17-64 bits RAM)
32 words (1-16 bits RAM)
32 words (17-64 bits RAM)
64 words (1-16 bits RAM)
64 words (17-64 bits RAM)
12

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