Datenblatt-pdf.com


GVT71256T18 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer GVT71256T18
Beschreibung (GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 24 Seiten
GVT71256T18 Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
327
CY7C1359A/GVT71256T18
256K x 18 Synchronous-Pipelined Cache Tag RAM
Features
• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
• Fast clock speed: 166, 150, 133, and 100 MHz
• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
• Pipelined data comparator
• Data input register load control by DEN
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• JTAG boundary scan
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low-profile JEDEC standard 100-pin TQFP package
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), Global Write (GW), and Data
Input Enable (DEN).
Asynchronous inputs include the Burst Mode Control (MODE),
the Output Enable (OE) and the Match Output Enable (MOE).
The data outputs (Q) and Match Output (MATCH), enabled by
OE and MOE respectively, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Data inputs are registered with Data Input Enable (DEN) and
chip enable pins (CE, CE2, and CE2). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of Clock (CLK).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to two bytes wide as controlled by the write control inputs. In-
dividual byte write allows individual byte to be written. WEL
controls DQ1DQ9. WEH controls DQ10DQ18. WEL and
WEH can be active only with BWE being LOW. GW being LOW
causes all bytes to be written.
The CY7C1359C/GVT71256T18 operates from a +3.3V pow-
er supply with output power supply being +2.5V or +3.3V. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 8 MB secondary cache.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1359A-166
71256T36-6
3.5
310
20
7C1359A-150
71256T36-6.7
3.8
275
20
7C1359A-133
71256T36-7.5
4.0
250
20
7C1359A-100
71256T36-10
4.5
190
20
www.DataSheet4U.com
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05120 Rev. **
Revised September 13, 2001






GVT71256T18 Datasheet, Funktion
CY7C1359A/GVT71256T18
Truth Table[5, 6, 7, 8, 9, 10, 11]
Operation
Address
Used CE CE2 CE2 ADSP ADSC
Deselected Cycle, Power Down None H X X
X
L
Deselected Cycle, Power Down None L X L
L
X
Deselected Cycle, Power Down None L H X
L
X
Deselected Cycle, Power Down None L X L
H
L
Deselected Cycle, Power Down None L H X
H
L
READ Cycle, Begin Burst
External L L H
L
X
READ Cycle, Begin Burst
External L L H
L
X
WRITE Cycle, Begin Burst
External L L H
H
L
READ Cycle, Begin Burst
External L L H
H
L
READ Cycle, Begin Burst
External L L H
H
L
READ Cycle, Continue Burst
Next
XX X
H
H
READ Cycle, Continue Burst
Next
XX X
H
H
READ Cycle, Continue Burst
Next H X X
X
H
READ Cycle, Continue Burst
Next H X X
X
H
WRITE Cycle, Continue Burst
Next X X X
H
H
WRITE Cycle, Continue Burst
Next H X X
X
H
READ Cycle, Suspend Burst
Current X X X
H
H
READ Cycle, Suspend Burst
Current X X X
H
H
READ Cycle, Suspend Burst
Current H X X
X
H
READ Cycle, Suspend Burst
Current H X X
X
H
WRITE Cycle, Suspend Burst Current X X X
H
H
WRITE Cycle, Suspend Burst Current H X X
X
H
ADV
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Partial Truth Table for READ/WRITE[12]
Function
GW BWE
WEH
WEL
READ
HH X X
READ
HL
HH
WRITE one byte
HL
LH
WRITE all bytes
HL L L
WRITE all bytes
LX X X
Notes:
7. X means Dont Care.H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH. It is assumed in this truth table that DEN is LOW.
8. WEL enables write to DQ1DQ9. WEH enables write to DQ10DQ18.
9. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
10. Suspending burst generates wait cycle.
11. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
12. X means dont care.H means logic HIGH. L means logic LOW. It is assumed in this truth table that chip is selected and ADSP is HIGH along with DEN being LOW.
Document #: 38-05120 Rev. **
Page 6 of 24

6 Page









GVT71256T18 pdf, datenblatt
TAP Timing and Test Conditions
TDO
Z0 = 50
5020 pF
Vt = 1.5V
(Fai)gure 5
TAP AC OUTPUT LOAD EQUIVALENT
tTHTH
TEST CLOCK
(TCK)
TEST MODE SELECT
(TMS)
tMVTH tTHMX
TEST DATA IN
(TDI)
tDVTH tTHDX
TEST DATA OUT
(TDO)
CY7C1359A/GVT71256T18
ALL INPUT PULSES
3.0V
1.5V
VSS 1.0 ns
1.0 ns
tTHTL
tTLTH
tTLQV
tTLQX
Document #: 38-05120 Rev. **
Page 12 of 24

12 Page





SeitenGesamt 24 Seiten
PDF Download[ GVT71256T18 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GVT71256T18(GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAMCypress Semiconductor
Cypress Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche