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GVT71512ZC18 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer GVT71512ZC18
Beschreibung (GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 30 Seiten
GVT71512ZC18 Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
256K x 36/512K x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200, 166, 133, 100 MHz
• Fast access time: 3.2, 3.6, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single WEN (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte Write (BWa–BWd) control (may be tied
LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
•Automatic power-down feature available using ZZ mode
or CE select
• JTAG boundary scan
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array), and 100-pin TQFP packages
Functional Description
The CY7C1354A/GVT71256ZC36 and CY7C1356A/
GVT71512ZC18 SRAMs are designed to eliminate dead
cycles when transitioning from Read to Write or vice versa.
These SRAMs are optimized for 100% bus utilization and
achieve Zero Bus Latency(ZBL)/No Bus Latency
(NoBL). They integrate 262,144 × 36 and 524,288 × 18
SRAM cells, respectively, with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. These employ high-speed, low-power CMOS
designs using advanced triple-layer polysilicon, double-layer
metal technology. Each memory cell consists of four
transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and Read-Write Control (WEN). BWc and BWd
apply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A clock enable (CEN) pin allows operation of the
CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CEN) is HIGH and the internal device
registers will hold their previous values.
There are three chip enable pins (CE, CE2, CE3) that allow the
user to deselect the device when desired. If any one of these
three are not active when ADV/LD is LOW, no new memory
operation can be initiated and any burst cycle in progress is
stopped. However, any pending data transfers (Read or Write)
will be completed. The data bus will be in high-impedance
state two cycles after chip is deselected or a Write cycle is
initiated.
The CY7C1354A/GVT71256ZC36 and CY7C1356A/
GVT71512ZC18 have an on-chip two-bit burst counter. In the
burst mode, the CY7C1354A/GVT71256ZC36 and
CY7C1356A/GVT71512ZC18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
Maximum Access Time
Maximum Operating Current
Commercial
Maximum CMOS Standby Current Commercial
7C1354A-200
71256ZC36-5
7C1356A-200
71512ZC18-5
3.2
560
30
7C1354A-166
71256ZC36-6
7C1356A-166
71512ZC18-6
3.6
480
30
7C1354A-133 7C1354A-100
71256ZC36-7.5 71256ZC36-10
7C1356A-133 7C1356A-100
71512ZC18-7.5 71512ZC18-10
4.2 5.0
410 350
30 30
Unit
ns
mA
mA
www.DataSheet4U.com
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
wwDwo.DcautmaSehnete#t4: U3.8c-o0m5161 Rev. *B
Revised April 25, 2002






GVT71512ZC18 Datasheet, Funktion
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Descriptions256K × 36 (continued)
256K × 36
TQFP Pins
256K × 36 Pin
PBGA Pins Name
Type
51, 52, 53, 56- (a) 6P, 7P, 7N,
59, 62, 63 6N, 6M, 6L, 7L,
68, 69, 72-75, 6K, 7K,
78, 79, 80 (b) 7H, 6H, 7G,
1, 2, 3, 6-9, 12, 6G, 6F, 6E, 7E,
13 7D, 6D,
18, 19, 22-25, (c) 2D, 1D, 1E,
28, 29, 30 2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
DQa
DQb
DQc
DQd
38 2U TMS
39 3U TDI
43 4U TCK
42 5U TDO
Input/
Output
Input
Output
14, 15, 16, 41, 4C, 2J, 4J, 6J, VCC
65, 66, 91
4R, 5R
5, 10, 17, 21, 3D, 5D, 3E, 5E,
26, 40, 55, 60, 3F, 5F, 3H, 5H,
67, 71, 76, 90 3K, 5K, 3M,
5M, 3N, 5N, 3P,
5P
VSS
4, 11, 20, 27, 1A, 7A, 1F, 7F, VCCQ
54, 61, 70, 77 1J, 7J, 1M, 7M,
1U, 7U
84 4A, 1B, 7B, 1C, NC
7C, 4D, 3J, 5J,
4L, 1R, 7R, 1T,
2T, 6T, 6U
Supply
Ground
I/O Supply
Pin Description
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte ais DQa pins;
Byte bis DQb pins; Byte cis DQc pins; Byte dis DQd pins.
IEEE 1149.1 Test Inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or be
connected to VCC.
IEEE 1149.1 Test Output: LVTTL-level output. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect).
Power Supply: +3.3V 5% and +5%.
Ground: GND.
Output Buffer Supply: +3.3V 0.165V and +0.165V for 3.3V I/O. +2.5V
0.125V and +0.4V for 2.5V I/O.
No Connect: These signals are not internally connected. It can be left
floating or be connected to VCC or to GND.
Pin Descriptions512K × 18
512K × 18
TQFP Pins
512K × 18 Pin
PBGA Pins Name
Type
Pin Description
37, 4P A0, Input- Synchronous Address Inputs: The address register is triggered by a
36, 4N A1, Synchronous combination of the rising edge of CLK, ADV/LD LOW, CEN LOW, and
32, 33, 34, 35, 2A, 3A, 5A, 6A, A
true chip enables. A0 and A1 are the two least significant bits of the
44, 45, 46, 47, 3B, 5B, 6B, 2C,
address field and set the internal burst counter if burst cycle is initiated.
48, 49, 50, 80, 3C, 5C, 6C, 4G,
81, 82, 83, 99, 2R, 6R, 2T, 3T,
100 5T, 6T
93, 5L BWa, Input- Synchronous Byte Write Enables: Each nine-bit byte has its own
94, 3G BWb Synchronous active LOW byte Write enable. On load Write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins. BWx can
all be tied LOW if always doing Write to the entire 18-bit word.
87
4M
CEN
Input- Synchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
Document #: 38-05161 Rev. *B
Page 6 of 31

6 Page









GVT71512ZC18 pdf, datenblatt
1 TEST-LOGIC
RESET
0
0 REUN-TEST/ 1
IDLE
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
SELECT
DR-SCAN
0
1
CAPTURE-DR
1
0
SHIFT-DR
0
1
EXIT1-DR
1
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
SELECT
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
EXIT2-IR
1
UPDATE-IR
1
0
1
0
1
0
Figure 1. TAP Controller State Diagram[21]
Note:
21.The 0/1next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05161 Rev. *B
Page 12 of 31

12 Page





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