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GVT7C1325A Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer GVT7C1325A
Beschreibung (GVT71256E18 / GVT7C1325A) 256K x 18 Synchronous Flow Through Burst SRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 16 Seiten
GVT7C1325A Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
325A
CY7C1325A/GVT71256E18
256K x 18 Synchronous Flow-Through Burst SRAM
Features
• Fast access times: 7.5 and 8 ns
• Fast clock speed: 117 and 100 MHz
• Provide high-performance 2-1-1-1 access rate
• Fast OE access times: 4.0 ns
• 3.3V –5% and +10% power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1325A/GVT71256E18 SRAM integrates
262,144x18 SRAM cells with advanced synchronous periph-
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE), and Sleep Mode Control (ZZ).
The data outputs (DQ), enabled by OE, are also asynchro-
nous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. WEL con-
trols DQ1DQ8 and DQP1. WEH controls DQ9DQ16 and
DQP2. WEL and WEH can be active only with BWE being
LOW. GW being LOW causes all bytes to be written.
The CY7C1325A/GVT71256E18 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PCsystems and for systems that benefit from a wide syn-
chronous data bus.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1325A-117
71256E18-7
7.5
370
10
7C1325A-100
71256E18-8
8
320
10
7C1325A-100
71256E18-9
8
320
10
7C1325A-100
71256E18-10
8
320
10
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
www.DataSheet4U.com
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05118 Rev. **
Revised September 12, 2001






GVT7C1325A Datasheet, Funktion
CY7C1325A/GVT71256E18
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power Down None
HXX
X
LX
X X L-H High-Z
Deselected Cycle, Power Down None
LXL
L
XX
X X L-H High-Z
Deselected Cycle, Power Down None
LHX
L
XX
X X L-H High-Z
Deselected Cycle, Power Down None
LXL
H
LX
X X L-H High-Z
Deselected Cycle, Power Down None
LHX
H
LX
X X L-H High-Z
READ Cycle, Begin Burst
External L L H
L
XX
X L L-H Q
READ Cycle, Begin Burst
External L L H
L
XX
X H L-H High-Z
WRITE Cycle, Begin Burst
External L
LH
H
LX
L X L-H D
READ Cycle, Begin Burst
External L
LH
H
L
X
H L L-H Q
READ Cycle, Begin Burst
External L
LH
H
L
X
H H L-H High-Z
READ Cycle, Continue Burst
Next
XXX
H
H
L
H L L-H Q
READ Cycle, Continue Burst
Next
XXX
H
H
L
H H L-H High-Z
READ Cycle, Continue Burst
Next
HXX
X
HL
H L L-H Q
READ Cycle, Continue Burst
Next
HXX
X
HL
H H L-H High-Z
WRITE Cycle, Continue Burst
Next
XXX
H
H
L
L X L-H D
WRITE Cycle, Continue Burst
Next
HXX
X
H
L
L X L-H D
READ Cycle, Suspend Burst
Current X X X
H
HH
H L L-H Q
READ Cycle, Suspend Burst
Current X X X
H
HH
H H L-H High-Z
READ Cycle, Suspend Burst
Current H X X
X
HH
H L L-H Q
READ Cycle, Suspend Burst
Current H X X
X
HH
H H L-H High-Z
WRITE Cycle, Suspend Burst
Current
XXX
H
HH
L
X L-H
D
WRITE Cycle, Suspend Burst
Current
HXX
X
HH
L
X L-H
D
Notes:
2. X means Dont Care.H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE +
WEL*WEH]*GW equals HIGH.
3. WEL enables write to DQ1DQ8 and DQP1. WEH enables write to DQ9DQ16 and DQP2.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification
Document #: 38-05118 Rev. **
Page 6 of 16

6 Page









GVT7C1325A pdf, datenblatt
CY7C1325A/GVT71256E18
Timing Diagrams (continued)
Read/Write Timing[24]
CLK
ADSP#
ADSC#
ADDRESS
WEH#, WEL#,
BWE#, GW#
CE#
(See Note)
tS
tH
tS
A1 A2
tH
ADV#
A3
A4
A5
OE#
DQ
Q(A1)
Q(A2)
Single Reads
D(A3)
Single Write
Q(A4)
Q(A4+1) Q(A4+2) Q(A4+3)
Burst Read
D(A5)
D(A5+1)
Burst Write
Document #: 38-05118 Rev. **
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