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GVT7C1361A Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer GVT7C1361A
Beschreibung (GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 28 Seiten
GVT7C1361A Datasheet, Funktion
( DataSheet : www.DataSheet4U.com )
1CY7C1361A
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
Features
• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
• Fast clock speed: 150, 133, 117, and 100 MHz
• 1 ns set-up time and hold time
• Fast OE access times: 3.5 ns and 4.0 ns
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The GVT71256B36/CY7C1361A and GVT71512B18/
CY7C1363A SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a positive-
edge-triggered Clock Input (CLK). The synchronous inputs in-
clude all addresses, all data inputs, address-pipelining Chip
Enable (CE), depth-expansion Chip Enables (CE2 and CE2),
Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables
(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).
However, the CE2 chip enable input is only available for TA(GV-
TI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The GVT71256B36 and GVT71512B18 operate from a +3.3V
power supply. All inputs and outputs are LVTTL compatible.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1361A-150
7C1363A-150
71256B36-6
71512B18-6
6.0
400
10
7C1361A-133
7C1363A-133
71256B36-6.5
71512B18-6.5
6.5
360
10
7C1361A-117
7C1363A-117
71256B36-7
71512B18-7
7.0
320
10
7C1361A-100
7C1363A-100
71256B36-8
71512B18-8
8.0
270
10
www.DataSheet4U.com
wwwC.yDparteaSssheSete4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 11, 2001






GVT7C1361A Datasheet, Funktion
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions (continued)
x36 PBGA Pins
(a) 6P, 7P, 7N,
6N, 6M, 6L, 7L,
6K, 7K,
(b) 7H, 6H, 7G,
6G, 6F, 6E, 7E,
7D, 6D,
(c) 2D, 1D, 1E,
2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
2U
3U
4U
5U
4C, 2J, 4J, 6J,
4R
3D, 5D, 3E, 5E,
3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M,
3N, 5N, 3P, 5P
1A, 7A, 1F, 7F,
1J, 7J, 1M, 7M,
1U, 7U
1B, 7B, 1C, 7C,
4D, 3J, 5J, 4L,
1R, 5R, 7R, 1T,
2T, 6T, 6U
x36 QFP Pins
(a) 51, 52, 53,
56, 57, 58, 59,
62, 63
(b) 68, 69, 72,
73, 74, 75, 78,
79, 80
(c) 1, 2, 3, 6, 7,
8, 9, 12, 13
(d) 18, 19, 22,
23, 24, 25, 28,
29, 30
38
39
43
for BG/B and
A/T version
42
for BG/B and
A/T version
15, 41,65, 91
5, 10, 17, 21,
26, 40, 55, 60,
67, 71, 76, 90
4, 11, 20, 27,
54, 61, 70, 77
14, 16, 66
38, 39, 42 for
AJ/TA Version
Pin
Name
DQa
DQb
DQc
DQd
TMS
TDI
TCK
TDO
VCC
VSS
VCCQ
NC
Type
Input/
Output
Input
Output
Supply
Ground
I/O Supply
-
Description
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet set
up and hold times around the rising edge of CLK.
IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for
AJ/TA package version.
IEEE 1149.1 test output. LVTTL-level output. Not available for
AJ/TA package version.
Core power Supply: +3.3V –5% and +10%
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
512K X 18 Pin Descriptions
x18 PBGA Pins X18 QFP Pins
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
3C, 5C, 6C, 2R,
6R, 2T, 3T, 5T,
6T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46,
45, 44, 49, 50
92 (A/T version)
43 (AJ/TA ver-
sion)
5L 93
3G 94
4M 87
Pin
Name
A0
A1
A
BWa
BWb
BWE
Type
Description
Input-
Synchronous
Addresses: These inputs are registered and must meet the set
up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle
and HIGH for a READ cycle. BWa controls DQa. BWb controls
DQb. Data I/O are high impedance if either of these inputs are
LOW, conditioned by BWE being LOW.
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set up and hold times around the rising edge
of CLK.
6

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GVT7C1361A pdf, datenblatt
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
1 TEST-LOGIC
RESET
0
0 REUN-TEST/ 1
IDLE
SELECT
DR-SCAN
0
1
CAPTURE-DR
1
0
SHIFT-DR
0
1
EXIT1-DR
1
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
SELECT
IR-SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
EXIT2-IR
1
UPDATE-IR
1
0
1
0
1
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
12

12 Page





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