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EM6125 Schematic ( PDF Datasheet ) - EM Microelectronic

Teilenummer EM6125
Beschreibung Digitally programmable 65 and 81 multiplex rate LCD Controller and Driver
Hersteller EM Microelectronic
Logo EM Microelectronic Logo 




Gesamt 30 Seiten
EM6125 Datasheet, Funktion
EM MICROELECTRONIC - MARIN SA
EM6125
Digitally programmable 65 and 81 multiplex rate LCD
Controller and Driver
Features
Slim IC for COG, COF and COB technologies
I2C & Serial bus interface
Internal display data RAM
2 digitally programmable multiplex rates :
- 81 rows x 102 columns
- 65 rows x 118 columns
LCD supply voltage internally generated and digitally
programmable from 3V to 11V
Low operating current consumption: 120µA (typ)
No external components needed except one VLCD
capacitor
On chip
- 4 intermediate bias voltages generation
- Oscillator for LCD refresh (no external components
required)
High noise immunity on inputs
Row and column drivers mirroring for COG or COF
connections flexibility
Partial display mode with 17 active rows for current
consumption reduction
Sleep mode for a nearly null current consumption
Wide VDD supply voltage from 1.8V to 5V.
Wide temperature range: -40°C to +85°C
Description
The EM6125 is a bit map controller and driver for full dot
matrix monochrome STN LCD displays. The driving
capability is 81 rows x 102 columns (10 rows of
characters + one row of icons) or 65 rows x 118 columns
(8 rows of characters + one row of icons). There is a one
to one relation between LCD pixels and bits of the
Display Data RAM.
The EM6125 is extremely low power consumption LCD
controller and driver product. The typical current
consumption is about 120µA with no external component
except the capacitor connected to VLCD. One important
feature on EM6125 is the partial display mode, which
enables important current consumption reduction. With
this function selected, only 17 rows remain active,
needed VLCD decreases and the commutation
frequencies of row and column drivers are also
decreased. These three effects of partial display mode
reduce drastically current consumption.
Typical Applications
Mobile phones
Smart cards
Automotive displays
Portable, battery operated products
Balances and scales, utility meters
Typical Operating Configuration
41 row drivers
40 row drivers
102 columns outputs
EM6125
VLCD SCL SDA RES Vss1 Vss2 VDD1 VDD2 VHV
Pin Configuration
Figure 1
Copyright 2001, EM Microelectronic-Marin SA
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Figure 2
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EM6125 Datasheet, Funktion
EM6125
VSS1,2 = 0V, VDD1 = VDD2 = 2.5V, VHV = 2.4V, TA = -40°C to +85 °C unless otherwise specified.
Parameter
Minimum reset pulse width
I2C timing characteristics
SCL frequency
SCL low period
SCL high period
SDA setup time
SDA hold time
SCL and SDA rise time
SCL and SDA fall time
Setup time for a repeated
start condition
Hold time for a
start condition
Setup time for a
stop condition
Spike width on SCL and SDA
Symbol
tRW
fSCL
tLOW
tHIGH
tSUDAT
tHDDAT
tR
tF
tSUSTA
tHDSTA
tSUSTO
tSW
Test conditions
Min.
50
Typ.
190
60
10
20
20
20
20
Time before a new transmission can start
tBUF
40
Capacitive bus line load
Serial bus timing characteristics
SCL frequency
SCL low period
SCL high period
SDA setup time
SDA hold time
SCL rise time
SCL fall time
CS setup time
CS hold time
Time before a new transmission can
start, CS minimum high time.
Cb
fSCL
tCL
tCH
tDS
tDH
tCR
tCF
tSUCS
tHDCS
tBUFCS
50
80
15
40
10
80
50
Max. Units
2100
200
200
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 ns
ns
400 pF
5.2 MHz
ns
ns
ns
ns
200 ns
200 ns
ns
ns
ns
Copyright 2001, EM Microelectronic-Marin SA
6
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6 Page









EM6125 pdf, datenblatt
CS
start
EM6125
stop
Control Byte
Data Byte
C0 = 1
Command byte
DC = 0
2n bytes
Control Byte
Data Byte
C0 = 1 DDRAMData byte
DC = 1
2n bytes
Figure 11: serial interface protocol
Control Byte
C0 = 0
DC = 1
Data Byte
DDRAMData byte
n bytes
Data byte is transferred with MSB bit first, LSB bit last:
MSB
LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
If CS goes high during a byte transfer, this byte is invalid but all previously transmitted data are valid. While CS is high the
serial interface is kept in reset that means internal interface counter and disables data transfer. To prevent transmission
errors, CS should be at high level when transfer is stopped.
Copyright 2001, EM Microelectronic-Marin SA
12
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12 Page





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