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PDF P5Z22V10 Data sheet ( Hoja de datos )
| Número de pieza | P5Z22V10 | |
| Descripción | 5V Zero Power / Total CMOS Universal PLD Device | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
P5Z22V10
5V zero power, TotalCMOS™,
universal PLD device
Product specification
Supersedes data of 1997 Apr 04
IC27 Data Handbook
1997 May 02
Philips
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www.DataSheet4U.com
1 page  
Philips Semiconductors
5V zero power, TotalCMOS™, universal PLD device
Product specification
P5Z22V10
CLK/I0
1
I1 – I11
11
PROGRAMMABLE AND ARRAY
(44 × 132)
8 10 12 14 16 16 14 12 10
8
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
OUTPUT
MACRO
CELL
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9
Figure 1. Functional Diagram
SP00060A
FUNCTIONAL DESCRIPTION
The P5Z22V10 implements logic functions as sum-of-products
expressions in a programmable-AND/fixed-OR logic array.
User-defined functions are created by programming the connections
of input signals into the array. User-configurable output structures in
the form of I/O macrocells further increase logic flexibility.
ARCHITECTURE OVERVIEW
The P5Z22V10 architecture is illustrated in Figure 1. Twelve
dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs
for creation of logic functions. At the core of the device is a
programmable electrically-erasable AND array which drives a
fixed-OR array. With this structure, the P5Z22V10 can implement up
to 10 sum-of-products logic expressions.
Associated with each of the 10 OR functions is an I/O macrocell
which can be independently programmed to one of 4 different
configurations. The programmable macrocells allow each I/O to
create sequential or combinatorial logic functions with either
Active-High or Active-Low polarity.
AND/OR Logic Array
The programmable AND array of the P5Z22V10 (shown in the Logic
Diagram) is formed by input lines intersecting product terms. The
input lines and product terms are used as follows:
44 input lines:
– 24 input lines carry the True and Complement of the signals
applied to the 12 input pins
– 20 additional lines carry the True and Complement values of
feedback or input signals from the 10 I/Os
132 product terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16)
used to form logical sums
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset product term
– 1 global asynchronous clear product term
At each input-line/product-term intersection there is an EEPROM
memory cell which determines whether or not there is a logical
connection at that intersection. Each product term is essentially a
44-input AND gate. A product term which is connected to both the
True and Complement of an input signal will always be FALSE, and
thus will not affect the OR function that it drives. When all the
connections on a product term are opened, a Don’t Care state exists
and that term will always be TRUE.
Variable Product Term Distribution
The P5Z22V10 provides 120 product terms to drive the 10 OR
functions. These product terms are distributed among the outputs in
groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic
Diagram). This distribution allows optimum use of device resources.
1997 May 02
5
5 Page 
Philips Semiconductors
5V zero power, TotalCMOS™, universal PLD device
TEST LOAD CIRCUIT
VCC +5V S1
C1 C2
INPUTS
I0 F0
DUT
In Fn
CK OE
GND
R1
R2 CL
NOTE:
C1 and C2 are to bypass VCC to GND.
R1 = 300Ω, R2 = 390Ω, CL = 35pF.
THEVENIN EQUIVALENT
SP00481
VL = 2.83V
170Ω
DUT OUTPUT
35pF
VOLTAGE WAVEFORM
SP00482
+3.0V
90%
10%
0V
1.5ns
tR tF
1.5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
1997 May 02
11
Product specification
P5Z22V10
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet P5Z22V10.PDF ] | |
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