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EP2S90xxx Schematic ( PDF Datasheet ) - Altera

Teilenummer EP2S90xxx
Beschreibung (EP2Sxxx) Stratix II Device Family
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EP2S90xxx Datasheet, Funktion
Section I. Stratix II Device
Family Data Sheet
This section provides designers with the data sheet specifications for
Stratix® II devices. They contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
Chapter 1. Introduction
Chapter 2. Stratix II Architecture
Chapter 3. Configuration & Testing
Chapter 4. Hot Socketing, ESD & Power-On Reset
Chapter 5. DC & Switching Characteristics
Chapter 6. Reference & Ordering Information
Revision History The table below shows the revision history for Chapters 1 through 6.
Chapter Date / Version
Changes Made
1 March 2005, 2.1 Updated “Introduction” and “Features” sections.
January 2005, v2.0 Added note to Table 1–2.
October 2004, v1.2 Updated Tables 1–2, 1–3, and 1–4.
July 2004, v1.1
Updated Tables 1–1 and 1–2.
Updated “Features” section.
www.DataSheet4U.comFebruary 2004, v1.0 Added document to the Stratix II Device Handbook.
Altera Corporation
www.DataSheet4U.com
Section I–1
Preliminary






EP2S90xxx Datasheet, Funktion
Features
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support on up to 156 channels with DPA
circuitry for 1-Gbps performance
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
Table 1–1. Stratix II FPGA Family Features
Feature
ALMs
Adaptive look-up tables (ALUTs) (1)
Equivalent LEs (2)
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
Total RAM bits
DSP blocks
18-bit × 18-bit multipliers (3)
Enhanced PLLs
Fast PLLs
Maximum user I/O pins
EP2S15
6,240
12,480
15,600
104
78
0
419,328
12
48
2
4
366
EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
13,552 24,176 36,384 53,016 71,760
27,104 48,352 72,768 106,032 143,520
33,880 60,440 90,960 132,540 179,400
202 329 488 699 930
144 255 408 609 768
12469
1,369,728 2,544,192 4,520,488 6,747,840 9,383,040
16 36 48 63 96
64 144 192 252 384
24444
48888
500
718
902
1,126
1,170
Notes to Table 1–1:
(1) One ALM contains two ALUTs. The ALUT is the cell used in the Quartus II software for logic synthesis.
(2) This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
(3) These multipliers are implemented using the DSP blocks.
1–2
Stratix II Device Handbook, Volume 1
Altera Corporation
March 2005

6 Page









EP2S90xxx pdf, datenblatt
Logic Array Blocks
Figure 2–2. Stratix II LAB Structure
Row Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
ALMs
Direct link
interconnect from
adjacent block
Local Interconnect LAB
Direct link
interconnect to
adjacent block
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven
by column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or DSP blocks from the left and right can also drive an LAB's local
interconnect through the direct link connection. The direct link
connection feature minimizes the use of row and column interconnects,
providing higher performance and flexibility. Each ALM can drive
24 ALMs through fast local and direct link interconnects. Figure 2–3
shows the direct link connection.
2–4
Stratix II Device Handbook, Volume 1
Altera Corporation
March 2005

12 Page





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