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PDF PD6729 Data sheet ( Hoja de datos )
| Número de pieza | PD6729 | |
| Descripción | PCI to PC Card Controller | |
| Fabricantes | Intel Corporation | |
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PD6729
PCI-to-PC Card (PCMCIA) Controller
Datasheet
The PD6729 is a single-chip PC Card (PCMCIA) controller solution capable of controlling two
fully independent PCMCIA sockets. The chip is fully PCMCIA-2.1 and JEIDA-4.1 compliant
and is optimized for use in embedded applications and notebook/handheld/mobile computer
systems where reduced form factor and low power consumption are critical design objectives.
With the PD6729, a complete dual-socket PCMCIA solution with power-control logic can
occupy less than 2 square inches (excluding connectors).
The PD6729 chip employs energy-efficient, mixed-voltage technology that can reduce system
power consumption by over 50 percent. The chip also provides a Suspend mode, which stops the
internal clock, and an automatic Low-power Dynamic mode, which stops transactions on the
PCMCIA bus, stops internal clock distribution, and turns off much of the internal circuitry.
PC applications typically access PC cards through the socket/card-services software interface.
To assure full compatibility with existing socket/card-services software and PC-card
applications, the register set in the PD6729 is a superset of the Intel 82365SL register set.
The chip provides fully buffered PCMCIA interfaces, meaning that no external logic is required
for buffering signals to/from the interface, and power consumption can be controlled by limiting
signal transitions on the PCMCIA bus.
www.DataSheet4U.com
As of May 2001, this document replaces the Basis Communications Corp.
document CL-PD6729 — PCI-to-PCMCIA Host Adapter.
www.DataSheet4U.com
May 2001
1 page  
PCI-to-PC Card (PCMCIA) Controller — PD6729
14.0
15.0
Bit Index
13.3.4 PCMCIA Bus Timing ...........................................................................102
Package Dimensions ............................................................................................108
14.1 208-Pin MQFP Package Outline Drawing .........................................................108
14.2 208-Pin LQFP Package Outline Drawing ..........................................................109
Ordering Information ............................................................................................110
....................................................................................................................................... 111
Figures
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4
5
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7
8
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10
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12
13
14
15
16
17
18
19
20
21
System Block Diagram .......................................................................................... 9
PC Card Controller Form Factor .........................................................................10
PD6729 Pin Diagram...........................................................................................13
Memory Window Organization ............................................................................25
I/O Window Organization ....................................................................................26
A Typical ZV Port Implementation.......................................................................27
A Common Mapping of PD6729 Interrupt Pins to
System Interrupt Signals .....................................................................................28
Indexed 8-Bit Register Structure .........................................................................32
Indexed 8-Bit Register Example..........................................................................32
Operation Registers as PCI Double-Word I/O Space at
Base Address 0 Register (programmed at offset 10h) ........................................43
Socket/Register Index Space ..............................................................................44
Pulse Mode Interrupts .........................................................................................71
FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL# (PCI Bus)..............................97
IDSEL Timing in a Configuration Cycle (PCI Bus)............................................99
PAR Timing (PCI Bus)....................................................................................100
Pulse Mode Interrupt Timing .............................................................................100
Memory Read/Write Timing...............................................................................102
Word I/O Read/Write Timing .............................................................................104
PCMCIA Read/Write Timing when System is 8 Bit
(SBHE Tied High)..............................................................................................105
Normal Byte Read/Write Timing (that is, all other byte
accesses, including odd I/O cycles where -IOIS16 is low) ................................106
16-Bit System to 8-Bit I/O Card: Odd Byte Timing ............................................107
Tables
1
2
3
4
5
6
7
8
9
10
PCI Bus Interface Pins ........................................................................................15
Socket Interface Pins ..........................................................................................18
Power Control and General Interface Pins..........................................................20
Power, Ground, and No-Connect Pins ................................................................21
Pin Usage Summary ...........................................................................................22
PD6729 Power-Management Modes ..................................................................30
Index Registers ...................................................................................................44
Enabling of Socket Power Controls.....................................................................51
Enabling of Output Signals to Socket..................................................................51
Bit 5: Pull-Up Control...........................................................................................78
Datasheet
5
5 Page 
1.0
PCI-to-PC Card (PCMCIA) Controller — PD6729
General Conventions
The following general conventions apply to this document.
Bits within words and words within various memory spaces are generally numbered with a 0 (zero)
as the least-significant bit or word. For example, the least-significant bit of a byte is bit 0, while the
most-significant bit is bit 7.
In addition, number ranges for bit fields and words are presented with the most-significant value
first. Thus, when discussing a bit field within a register, the bit number of the most-significant bit is
written first, followed by a hyphen (-) and then the bit number of the least-significant bit; as in,
bits 7-0.
In this document, the names of the PD6729 internal registers are bold-faced. For example, Chip
Revision and Power Control are register names. The names of bit fields are written with initial
upper-case letters. For example, Card Power On and Battery Voltage Detect are bit field names.
Numbers and Units
The unit Kbyte designates 1024 bytes (210). The unit Mbyte designates 1,048,576 bytes (220). The
unit Gbyte designates 1,073,741,824 bytes (230). The unit Hz designates hertz. The unit kHz
designates 1000 hertz. The unit MHz designates 1,000,000 Hz. The unit ms designates millisecond.
The unit µs designates microsecond. The unit ns designates nanosecond. The unit mA designates
milliampere. The unit V immediately following a number designates volt.
Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For
example, 14h and 03CAh are hexadecimal numbers.
Binary numbers have the letter b appended to them or are enclosed in single quotation marks. For
example, 11b and ‘11’ are binary numbers.
Numbers not indicated by an h or b are decimal.
In addition, a capital letter X is used within numbers to indicate digits ignored by the PD6729
within the current context. For example, 101XX01b is a binary number with bits 3-2 ignored.
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PD6729.PDF ] | |
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