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EDE5104ABSE Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EDE5104ABSE
Beschreibung (EDE51xxABSE) 512M bits DDR2 SDRAM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
EDE5104ABSE Datasheet, Funktion
DATA SHEET
512M bits DDR2 SDRAM
EDE5104ABSE (128M words × 4 bits)
EDE5108ABSE (64M words × 8 bits)
EDE5116ABSE (32M words × 16 bits)
Description
The EDE5104ABSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108ABSE is a 512M bits DDR2 SDRAM
organized as 16,777,216 words × 8 bits × 4 banks.
They are packaged in 64-ball FBGA (µBGA) package.
The EDE5116ABSE is a 512M bits DDR2 SDRAM
organized as 8,388,608 words × 16 bits × 4 banks.
It is packaged in 84-ball FBGA (µBGA) package.
Features
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
SSTL_18 compatible I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0323E90 (Ver. 9.0)
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002-2005






EDE5104ABSE Datasheet, Funktion
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Recommended DC Operating Conditions (SSTL_18)
Parameter
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD
1.7
1.8 1.9
V4
Supply voltage for output
VDDQ
1.7
1.8 1.9
V4
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
Termination voltage
VTT
VREF 0.04
VREF
VREF + 0.04
V
3
DC input logic high
VIH (DC)
VREF + 0.125
VDDQ + 0.3
V
DC input low
VIL (DC)
0.3
VREF – 0.125 V
AC input logic high
VIH (AC)
VREF + 0.250
V
AC input low
VIL (AC)
VREF 0.250 V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and
VDDL tied together.
Data Sheet E0323E90 (Ver. 9.0)
6

6 Page









EDE5104ABSE pdf, datenblatt
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
AC Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
-5C
Frequency (Mbps)
533
Parameter
/CAS latency
Symbol min.
CL 4
Active to read or write command delay tRCD 15
Precharge command period
Active to active/auto refresh command
time
DQ output access time from CK, /CK
DQS output access time from CK, /CK
tRP 15
tRC 55
tAC 500
tDQSCK 450
CK high-level width
tCH 0.45
CK low-level width
CK half period
Clock cycle time
tCL 0.45
tHP
min.
(tCL, tCH)
tCK 3750
DQ and DM input hold time
tDH 225
DQ and DM input setup time
tDS
Control and Address input pulse width
for each input
tIPW
DQ and DM input pulse width for each
input
tDIPW
Data-out high-impedance time from
CK,/CK
tHZ
Data-out low-impedance time from
CK,/CK
tLZ
DQS-DQ skew for DQS and associated
DQ signals
tDQSQ
DQ hold skew factor
tQHS
100
0.6
0.35
tAC min.
DQ/DQS output hold time from DQS
Write command to first DQS latching
transition
DQS input high pulse width
tQH tHP – tQHS
tDQSS WL 0.25
tDQSH 0.35
DQS input low pulse width
tDQSL 0.35
DQS falling edge to CK setup time
tDSS 0.2
DQS falling edge hold time from CK tDSH 0.2
Mode register set command cycle time tMRD 2
Write preamble setup time
tWPRES 0
Write postamble
tWPST 0.4
Write preamble
tWPRE 0.25
Address and control input hold time
tIH
375
Address and control input setup time tIS
250
Read preamble
tRPRE 0.9
Read postamble
tRPST 0.4
Active to precharge command
tRAS 40
Active to auto-precharge delay
tRAP tRCD min.
max.
5
+500
+450
0.55
0.55
8000
-4A
400
min.
3
15
15
55
600
500
0.45
0.45
min.
(tCL, tCH)
5000
275
150
0.6
0.35
tAC max.
tAC max. tAC min.
300
400
tHP – tQHS
WL + 0.25 WL 0.25
0.6
1.1
0.6
70000
0.35
0.35
0.2
0.2
2
0
0.4
0.25
475
350
0.9
0.4
40
tRCD min.
max.
5
+600
+500
0.55
0.55
8000
tAC max.
tAC max.
350
450
WL + 0.25
0.6
1.1
0.6
70000
Unit Notes
tCK
ns
ns
ns
ps
ps
tCK
tCK
ps
ps
ps 5
ps 4
tCK
tCK
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps 5
ps 4
tCK
tCK
ns
ns
Data Sheet E0323E90 (Ver. 9.0)
12

12 Page





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