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DS12885 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS12885
Beschreibung (DS12xxx) Real Time Clock
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 27 Seiten
DS12885 Datasheet, Funktion
Rev 0; 6/05
Real-Time Clock
General Description
Features
The DS12885, DS12887, and DS12C887 real-time
clocks (RTCs) are designed to be direct replacements
for the DS1285 and DS1287. The devices provide a
Drop-In Replacement for IBM AT Computer
Clock/Calendar
real-time clock/calendar, one time-of-day alarm, three RTC Counts Seconds, Minutes, Hours, Day, Date,
maskable interrupts with a common interrupt output, a
Month, and Year with Leap Year Compensation
programmable square wave, and 114 bytes of battery-
backed static RAM (113 bytes in the DS12C887 and
DS12C887A). The DS12887 integrates a quartz crystal
and lithium energy source into a 24-pin encapsulated
mDIP package. The DS12C887 adds a century byte at
address 32h. For all devices, the date at the end of the
omonth is automatically adjusted for months with fewer
.cthan 31 days, including correction for leap years. The
devices also operate in either 24-hour or
12-hour format with an AM/PM indicator. A precision
temperature-compensated circuit monitors the status of
UVCC. If a primary power failure is detected, the device
t4automatically switches to a backup supply. A lithium
coin-cell battery can be connected to the VBAT input
pin on the DS12885 to maintain time and date operation
ewhen primary power is absent. The device is accessed
through a multiplexed byte-wide interface, which sup-
eports both Intel and Motorola modes.
hApplications
Embedded Systems
SUtility Meters
taSecurity Systems
Network Hubs, Bridges, and Routers
aTypical Operating Circuit
.DCRYSTAL
VCC
www eet4U.comDS83C520
X1 X2
AS
VCC
RESET
R/W RCLR
DS
CS DS12885
AD(0–7)
SQW
IRQ VBAT
MOT
GND
Through 2099
Binary or BCD Time Representation
12-Hour or 24-Hour Clock with AM and PM in
12-Hour Mode
Daylight Saving Time Option
Selectable Intel or Motorola Bus Timing
Interfaced with Software as 128 RAM Locations
14 Bytes of Clock and Control Registers
114 Bytes of General-Purpose, Battery-Backed
RAM (113 Bytes in the DS12C887 and
DS12C887A)
RAM Clear Function (DS12885, DS12887A, and
DS12C887A)
Interrupt Output with Three Independently
Maskable Interrupt Flags
Time-of-Day Alarm Once Per Second to Once
Per Day
Periodic Rates from 122µs to 500ms
End-of-Clock Update Cycle Flag
Programmable Square-Wave Output
Automatic Power-Fail Detect and Switch Circuitry
Optional 28-Pin PLCC Surface Mount Package or
32-Pin TQFP (DS12885)
Optional Encapsulated DIP (EDIP) Package with
Integrated Crystal and Battery (DS12887,
DS12887A, DS12C887, DS12C887A)
Optional Industrial Temperature Range Available
Underwriters Laboratory (UL) Recognized
ataShPin Configurations and Ordering Information appear at end of data sheet.
.D______________________________________________ Maxim Integrated Products 1
wwFor pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
w1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.






DS12885 Datasheet, Funktion
Real-Time Clock
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 2)
PARAMETER
Recovery at Power-Up
VCC Fall Time; VPF(MAX) to
VPF(MIN)
SYMBOL
tRPU
tF
CONDITIONS
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tR
DATA RETENTION
(TA = +25°C)
PARAMETER
Expected Data Retention
SYMBOL
tDR
CONDITIONS
MIN TYP MAX UNITS
20 200 ms
300 µs
0 µs
MIN TYP MAX UNITS
10 years
CAPACITANCE
(TA = +25°C) (Note 9)
PARAMETER
Capacitance on All Input Pins
Except X1 and X2
Capacitance on IRQ, SQW, and
DQ Pins
SYMBOL
CIN
CIO
CONDITIONS
MIN TYP MAX UNITS
5 pF
7 pF
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
Output Load Including Scope and Jig
Input and Output Timing Measurement Reference Levels
Input-Pulse Rise and Fall Times
TEST CONDITIONS
0 to 3.0V
50pF + 1TTL Gate
Input/Output: VIL maximum and VIH minimum
5ns
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1: RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage.
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: All outputs are open.
Note 5: Specified with CS = DS = R/W = RESET = VCC; MOT, AS, AD0–AD7 = 0; VBACKUP open.
Note 6: Applies to the AD0 to AD7 pins, the IRQ pin, and the SQW pin when each is in a high-impedance state.
Note 7: The MOT pin has an internal 20kpulldown.
Note 8: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 9: Guaranteed by design. Not production tested.
Note 10: Measured with a 50pF capacitance load.
6 _____________________________________________________________________

6 Page









DS12885 pdf, datenblatt
Real-Time Clock
Clock Accuracy
The accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise cou-
pled into the oscillator circuit can result in the clock run-
ning fast. Figure 2 shows a typical PC board layout for
isolation of the crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks for more detailed information.
Clock Accuracy for DS12887, DS12887A,
DS12C887, DS12C887A Only
The encapsulated DIP modules are trimmed at the fac-
tory to an accuracy of ±1 minute per month at +25°C.
Power-Down/Power-Up
Considerations
The real-time clock continues to operate, and the RAM,
time, calendar, and alarm memory locations remain
nonvolatile regardless of the VCC input level. VBAT must
remain within the minimum and maximum limits when
VCC is not applied. When VCC is applied and exceeds
VPF (power-fail trip point), the device becomes accessi-
ble after tREC—if the oscillator is running and the oscil-
lator countdown chain is not in reset (Register A). This
time allows the system to stablize after power is
applied. If the oscillator is not enabled, the oscillator-
enable bit is enabled on power-up, and the device
becomes immediately accessible.
Time, Calendar, and Alarm
Locations
The time and calendar information is obtained by read-
ing the appropriate register bytes. The time, calendar,
and alarm are set or initialized by writing the appropri-
ate register bytes. Invalid time or date entries result in
undefined operation. The contents of the 10 time, cal-
endar, and alarm bytes can be either binary or binary-
coded decimal (BCD) format.
The day-of-week register increments at midnight, incre-
menting from 1 through 7. The day-of-week register is
used by the daylight saving function, so the value 1 is
defined as Sunday. The date at the end of the month is
LOCAL GROUND PLANE (TOP LAYER)
CRYSTAL
X1
X2
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
Figure 2. Layout Example
GND
automatically adjusted for months with fewer than 31
days, including correction for leap years.
Before writing the internal time, calendar, and alarm reg-
isters, the SET bit in Register B should be written to logic
1 to prevent updates from occurring while access is
being attempted. In addition to writing the 10 time, calen-
dar, and alarm registers in a selected format (binary or
BCD), the data mode bit (DM) of Register B must be set
to the appropriate logic level. All 10 time, calendar, and
alarm bytes must use the same data mode. The SET bit
in Register B should be cleared after the data mode bit
has been written to allow the RTC to update the time and
calendar bytes. Once initialized, the RTC makes all
updates in the selected mode. The data mode cannot be
changed without reinitializing the 10 data bytes. Tables
2A and 2B show the BCD and binary formats of the time,
calendar, and alarm locations.
The 24-12 bit cannot be changed without reinitializing the
hour locations. When the 12-hour format is selected, the
higher-order bit of the hours byte represents PM when it
is logic 1. The time, calendar, and alarm bytes are always
accessible because they are double-buffered. Once per
second the seven bytes are advanced by one second
and checked for an alarm condition.
If a read of the time and calendar data occurs during
an update, a problem exists where seconds, minutes,
hours, etc., may not correlate. The probability of read-
ing incorrect time and calendar data is low. Several
methods of avoiding any possible incorrect time and
calendar reads are covered later in this text.
12 ____________________________________________________________________

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