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DP83848YB Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83848YB
Beschreibung PHYTER - Extreme Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
DP83848YB Datasheet, Funktion
Janusry 2006
DP83848YB PHYTER® - Extreme Temperature
Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description
Features
The number of applications requiring ethernet connec- Extreme Temperature from -40 °C to 125 °C
tivity continues to increase. Along with this increased Low-power 3.3V, 0.18µm CMOS technology
market demand is a change in application require-
ments. The DP83848YB was designed to allow ether-
Low power consumption < 270mW Typical
net connectivity in the harshest environments. Our 3.3V MAC Interface
device meets IEEE 802.3u standards over an Auto-MDIX for 10/100 Mb/s
EXTREME temperature range of -40°C to 125 °C. This Energy Detection Mode
device is ideally suited for harsh environments for
example wireless remote base stations, automo-
25 MHz clock out
tive/transportation and industrial control applications. SNI Interface (configurable)
The DP83848YB is a highly reliable, feature rich robust RMII Rev. 1.2 Interface (configurable)
device which includes enhanced ESD protection, MII MII Serial Management Interface (MDC and MDIO)
and RMII for maximum flexibility in MPU selection all in
a 48 pin LQFP package.
IEEE 802.3u MII
IEEE 802.3u Auto-Negotiation and Parallel Detection
With the DP83848YB NATIONAL continues to build on
its Ethernet expertise and leadership position by pro-
IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
viding the flexibility allowing for ease of implementation IEEE 802.3u PCS, 100BASE-TX transceivers and filters
by the end user.
IEEE 1149.1 JTAG
The DP83848YB features integrated sublayers to sup- Integrated ANSI X3.263 compliant TP-PMD physical sub-
port both 10BASE-T and 100BASE-TX Ethernet proto- layer with adaptive equalization and Baseline Wander com-
cols, which ensures compatibility and interoperability pensation
with all other standards based Ethernet solutions.
Error-free Operation up to 150 meters
Applications
Programmable LED support Link, 10 /100 Mb/s Mode, Activ-
ity, and Collision Detect
Automotive/Transportation
Industrial Controls and Factory Automation
General Embedded Applications
Single register access for complete PHY status
10/100 Mb/s packet BIST (Built in Self Test)
Lead free 48-pin LQFP package (7mm) x (7mm)
System Diagram
MPU/CPU
MII/RMII/SNI
DP83848YB
10/100 Mb/s
®
PHYTER is a registered trademark of National Semiconductor.
© 2006 National Semiconductor Corporation
25 MHz
Clock
Source
Status
LEDs
Typical Application
1
10BASE-T
or
100BASE-TX
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DP83848YB Datasheet, Funktion
List of Figures
Figure 1. DP83848YB Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . . . . 28
Figure 9. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 11. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Top View, Thermal Vias for GNDPAD, pin 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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DP83848YB pdf, datenblatt
1.5 JTAG Interface
Signal Name
TCK
TDI
TDO
TMS
TRST#
Type
I, PU
I, PU
O
I, PU
I, PU
1.6 Reset and Power Down
Pin #
8
12
9
10
11
Description
TEST CLOCK
This pin has a weak internal pullup.
TEST DATA INPUT
This pin has a weak internal pullup.
TEST OUTPUT
TEST MODE SELECT
This pin has a weak internal pullup.
TEST RESET: Active low asynchronous test reset.
This pin has a weak internal pullup.
Signal Name
RESET_N
PWR_DOWN/INT
Type
I, PU
I, OD, PU
Pin #
29
7
Description
RESET: Active Low input that initializes or re-initializes the
DP83848YB. Asserting this pin low for at least 1 µs will force a re-
set process to occur. All internal registers will re-initialize to their
default states as specified for each bit in the Register Block sec-
tion. All strap options are re-initialized as well.
See Section 5.5 for detailed description.
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and
should be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will
be asserted low when an interrupt condition occurs. Although the
pin has a weak internal pull-up, some applications may require an
external pull-up resister. Register access is required for the pin to
be used as an interrupt mechanism. See Section 5.5.2 Interrupt
Mechanism for more details on the interrupt mechanisms.
1.7 Strap Options
The DP83848YB uses many of the functional pins as strap
options. The values of these pins are sampled during reset
and used to strap the device into specific modes of opera-
tion. The strap option pin assignments are defined below.
The functional pin name is indicated in parentheses.
A 2.2 kresistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func-
tions after reset is deasserted, they should not be con-
nected directly to VCC or GND.
Signal Name
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)
Type
S, O, PU
S, O, PD
Pin #
42
43
44
45
46
Description
PHY ADDRESS [4:0]: The DP83848YB provides five PHY ad-
dress pins, the state of which are latched into the PHYCTRL reg-
ister at system Hardware-Reset.
The DP83848YB supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). A PHY Address of 0 puts the
part into the MII Isolate Mode. The MII isolate mode must be se-
lected by strapping Phy Address 0; changing to Address 0 by reg-
ister write will not put the Phy in the MII isolate mode. Please refer
to section 2.3 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
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