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PEB22554 Schematic ( PDF Datasheet ) - Siemens Semiconductor

Teilenummer PEB22554
Beschreibung ICs for Communications
Hersteller Siemens Semiconductor
Logo Siemens Semiconductor Logo 




Gesamt 30 Seiten
PEB22554 Datasheet, Funktion
ICs for Communications
Quad Framing and Line Interface Component for E1 / T1 / J1
QuadFALCTM
PEB 22554 Version 1.1
Preliminary Data Sheet 09.98
DS 1






PEB22554 Datasheet, Funktion
Quad Framing and Line Interface Component for E1/T1
QFALC
PEB 22554
CMOS
QuadFALC in E1 Mode
1 Features E1
Quad Line Interface
• High density, generic interface for all E1 / T1 / J1
applications
• Quad analog receive and transmit circuitry for long/ P-TQFP-144
short haul applications
• Data and clock recovery using an integrated
digital phase locked loop
• Maximum line attenuation up to -34 dB at 1024 kHz
adaptively controlled receive equalization network adjusts up to 4500 feet (PULP 22
AWG) in length, noise - and crosstalk -filter, line attenuation status
• Programmable transmit pulse shapes for E1 signals
• Programmable Line Build-Out according to FTZ221
• Low transmitter output impedances for high transmit return loss
• Tri-state function of the analog transmit line outputs
• Transmit line monitor protecting the device from damage
• Jitter specifications of ITU-T I.431 , G.703 , G.736 and G.823 met
• Crystal-less wander and jitter attenuation/compensation
• Low frequency reference clock: 2.048MHz
• Power down function per channel
• Dual rail or single rail digital inputs and outputs
• Unipolar NRZ or CMI for interfacing fibre optical transmission routes
• Selectable line codes (HDB3, AMI)
• Loss of signal indication with programmable thresholds according to ITU-T G.775
and ETS300233
• Clock generator for jitter free system/ transmit clocks per channel
• Local loop and remote loop for diagnostic purposes
• Ultra low power device , single power supply: 3.3 V
Type
PEB 22554-HT
Version
V1.1
Semiconductor Group
Ordering Code
Q67003H9339
6
Package
P-TQFP-144(SMD)
09.98

6 Page









PEB22554 pdf, datenblatt
2 Pin Descriptions E1
2.1 Pin Diagram
P-TQFP-144
PEB 22554
Pin Descriptions E1
XL1_1/XDOP1/XOID1
VDDX
XL2_1/XDON1/XFM1
TDI
TDO
VDDR
RL1_1/RDIP1/ROID1
RL2_1/RDIN1/RCLKI1
VSSR
N.C.
RCLK1
XPA1
XPB1
XPC1
XPD1
VDD
VSS
XPA2
XPB2
XPC2
XPD2
RCLK2
TRS
VDD
MCLK
N.C.
VSS
VSSR
RL2_2/RDIN2/RCLKI2
RL1_2/RDIP2/ROID2
VDDR
TCK
TMS
XL2_2/XDON2/XFM2
VDDX
XL1_2/XDOP2/XOID2
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
QuadFALCTM
PEB 22554
72 XL1_4/XDOP4/XOID4
71 VDDX
70 XL2_4/XDON4/XFM4
69 SEC/FSC
68 IM
67 VDDR
66 RL1_4/RDIP4/ROID4
65 RL2_4/RDIN4/RCLKI4
64 VSSR
63 N.C.
62 ALE
61 RCLK4
60 XPD4
59 XPC4
58 XPB4
57 XPA4
56 VSS
55 VDD
54 XPD3
53 XPC3
52 XPB3
51 XPA3
50 SCLKX4
49 XDI4
48 SYNC
47 RCLK3
46 RES
45 VSSR
44 RL2_3/RDIN3/RCLKI3
43 RL1_3/RDIP3/ROID3
42 VDDR
41 INT
40 DBW
39 XL2_3/XDON3/XFM3
38 VDDX
37 XL1_3/XDOP3/XOID3
ITP10391
Figure 4 Pin Configuration of QuadFALC
Note: All unused input pins have to be connected to a defined level (VSS / VDD).
Semiconductor Group
12
09.98

12 Page





SeitenGesamt 30 Seiten
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