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PDF DS1371 Data sheet ( Hoja de datos )
| Número de pieza | DS1371 | |
| Descripción | 32-Bit Binary Counter Watchdog Clock | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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heet4U.comwww.maxim-ic.com
DS1371
2-Wire, 32-Bit Binary Counter
Watchdog Clock
ataSGeneral Description
.DThe DS1371 is a 32-bit binary counter that is
wdesigned to continuously count time in seconds.
wAn additional counter that can generate a
wperiodic alarm or serve as a watchdog timer is
malso provided. If enabled as a watchdog timer,
the watchdog strobe input pin provides a
ohardware reset of the counter. If disabled, this
.ccounter can be used as 3 Bytes of general-
purpose RAM. A configurable output can be
used as an interrupt or provide a square wave at
Uone of four selectable frequencies. The device is
t4programmed serially through a 2-wire
bidirectional bus.
eeApplications
Servers
hPoint-of-Sale Equipment
Portable Instruments
SElapsed Time Measurements
Features
§ 32-Bit Binary Counter
§ 24-Bit Binary Counter Provides Periodic
Alarm, Watchdog Timer, or RAM
§ Strobe Input to Reset Watchdog Timer
§ Single Output Configurable as Interrupt or
Square Wave
§ 2-Wire Serial Interface
§ Low-Voltage Operation
§ Operating Temperature Range:
-40°C to +85°C
§ Available in 8-Pin mSOP
Ordering Information
PART
DS1371U
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
8 µSOP
TOP
MARK
DS1371
Pin Configuration
taTypical Operating Circuit
TOP VIEW
.Da X1
X2
w WDS
w GND
18
27
DS1371
36
45
VCC
SQW/INT
SCL
SDA
w .comµSOP
.DataSheet4UNote: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
www1 of 14
REV: 051203
1 page  
Figure 1. Timing Diagram
DS1371
Figure 2. Functional Diagram
5 of 14
5 Page 
DS1371
Status Register (08h)
Bit #
76
54
3
21
0
Name OSF 0 0 0 0 0 0 AF
Default
10
0 0 0 00—
Bit 7/Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or
was stopped for some period and can be used to judge the validity of the timekeeping data. This bit is set
to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the
OSF bit to be set:
· The first time power is applied.
· The voltage present on VCC is insufficient to support oscillation.
· The EOSC bit is turned off.
· External influences on the crystal (e.g., noise, leakage, etc.)
· This bit remains at logic 1 until written to logic 0.
Bit 0/Alarm Flag (AF). A logic 1 in the AF bit indicates that the WD/ALM counter reached 0. If INTCN
is set to a 1, and WD/ALM is set to 0 and AIE is set to 1, the SQW/INT pin goes low and stays low until
AF is cleared. AF is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to
write logic 1 leaves the value unchanged. If INTCN and WD/ALM are set to 1 and the AIE is set to 1, the
SQW/INT pin pulses low for 250ms when the WD/ALM counter reaches 0 and sets AF = 1. At the
completion of the 250ms pulse, the DS1371 clears the AF bit to a 0. If the 250ms pulse is active, writing
AF to a 0 does not truncate the pulse.
2-Wire Serial Interface
The DS1371 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1371 operates as a slave on the 2-wire bus.
Connections to the bus are made through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 5):
· Data transfer can be initiated only when the bus is not busy.
· During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.
11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS1371.PDF ] | |
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