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PCI6254 Schematic ( PDF Datasheet ) - PLX Technology

Teilenummer PCI6254
Beschreibung Dual Mode PCI to PCI Bridge
Hersteller PLX Technology
Logo PLX Technology Logo 




Gesamt 30 Seiten
PCI6254 Datasheet, Funktion
www.DataSheet4U.com
.comPCI 6254 (HB6)
Dual Mode
t4UUniversal PCI-to-PCI Bridge
eData Book
www.DataShe www.DataSheet4U.com






PCI6254 Datasheet, Funktion
HISTORY
Rev
Rev 0.1
Rev 0.2
Rev 0.3
Rev 0.4
Rev 0.9
Date
7/7/01
7/26/01
8/27/01
9/27/01
10/11/01
Description
First Marketing release of PCI 6254 data book
Second Marketing release of PCI 6254 data book
- corrected some typing mistakes.
Updated specifications
CLKRUN pins can be left unconnected in Transparent Mode if
CLKRUN mechanism is not enabled by software
Remove Private memory descriptions from Non-Transparent Mode
section. Private memory is only for Transparent Mode.
Corrected typing mistakes.
Added pin location list and corrected typing mistakes
Add pin list sorted by location and name
Clarify GPIO and clock control registers descriptions
Clarified Reset description in the Reset Chapter
Revision Code changed to 04h
Pre-production release
Added power management D3-D0 reset description
More detailed EERPOM option description
Add new chapter about PCI 6254 usage
Eng Chk Mkt Chk
Rev 0.91 11/5/01
Rev 0.92 12/4/01
Rev 0.93 1/8/02
Rev 1.0 1/18/02
Corrected EEPROM Clock register description
Corrected Table references
Corrections in Reset Chapter: PWRGD does NOT cause
P_RSTOUT# and S_RSTOUT# to go active and does NOT reset the
entire chip; Software chip reset does NOT cause IO signals to go
three-state and causes EEPROM load only in Non-Transparent
Mode; S_RSTIN# input is NOT used in Transparent Mode;
S_CLKSTB low will NOT cause Secondary port internal reset in
Non-Transparent Mode; PCI 6254 needs 512 clock to initialize the
bridge functions after any reset.
Added description about L_STATand EJECT.
Major modification to the RESET chapter about Non-Transparent
Mode reset mechanisms. The following are major the changes:
- Non-Transparent Mode P_RSTIN# will also reset secondary port
registers at 0-3fh.
- Non-Transparent Mode S_RSTIN# only resets secondary port
state machine, NOT registers.
- PWRGD initiated EEPROM autoload in Non-Transparent Mode
can only be effective if the PWRGD rising edge is aligned with or
come after P_RSTIN# rising edge. EEPROM chapter is also
updated to describe the requirement.
- Corrected Description on Power Management Initiated Reset
which will NOT cause P_RSTOUT# and S_RSTOUT#.
Updated specification on Register D8h, bit 4. The correct READ
back data is inverted while the Write data is not.
PCI 6254 Data Book v2.1
2003 PLX Technology, Inc. All rights reserved.
6

6 Page









PCI6254 pdf, datenblatt
18 FLOW THROUGH OPTIMIZATION............................................................................................................ 129
18.1 CAUTIONS WITH NON-OPTIMIZED PCI MASTER DEVICES ............................................................................. 129
18.2 READ CYCLE OPTIMIZATION ....................................................................................................................... 129
18.2.1 Primary/Secondary Initial Prefetch Count ........................................................................................ 130
18.2.2 Primary/Secondary Incremental Prefetch Count.............................................................................. 130
18.2.3 Primary/Secondary Maximum Prefetch Count ................................................................................. 130
18.3 READ PREFETCH BOUNDARIES ................................................................................................................... 130
19 NON-TRANSPARENT MODE .................................................................................................................... 131
19.1 NON-TRANSPARENT MODE CONFIGURATION SPACE MAP ............................................................................ 131
19.1.1 Configuration 80h-FFh, Shadow and Extended Registers............................................................... 132
19.1.1.1
Configuration 80h-FFh Registers..................................................................................................................... 132
19.1.1.2
Extended Register Map .................................................................................................................................. 134
19.1.1.3
Primary Configuration Shadow Registers ......................................................................................................... 135
19.2 NON-TRANSPARENT MODE PRIMARY CONFIGURATION REGISTERS DESCRIPTION ......................................... 136
19.2.1 PCI Standard Configuration Registers ............................................................................................. 136
19.2.2 Subsystem Vendor ID and Subsystem ID........................................................................................ 140
19.2.3 Secondary Port Standard PCI Configuration Registers Shadow ..................................................... 141
19.2.3.1
Prefetch Control Registers .............................................................................................................................. 147
19.2.4 Cross Bridge Configuration Access Control Registers..................................................................... 153
19.2.5 GPIO Registers ................................................................................................................................ 158
19.2.6 Direct Message Interrupt Registers.................................................................................................. 161
19.2.7 Message Signal Interrupt Registers ................................................................................................. 163
19.2.8 Doorbell and Miscellaneous Interrupt Registers .............................................................................. 164
19.2.9 Extended Registers .......................................................................................................................... 168
19.2.9.1
Address Translation Control Registers ............................................................................................................. 169
19.2.10
General Control Registers ............................................................................................................ 174
19.2.11
Power Management Registers ..................................................................................................... 175
19.2.12
Hot Swap Registers ...................................................................................................................... 178
19.2.13
VPD Registers .............................................................................................................................. 179
19.3 NON-TRANSPARENT MODE OPERATION ...................................................................................................... 180
19.4 INTERRUPTS .............................................................................................................................................. 181
19.4.1 Direct Message Interrupts ................................................................................................................ 181
19.4.1.1
Direct Message Interrupt Operations................................................................................................................ 181
19.4.2 Doorbell Interrupts............................................................................................................................ 181
19.4.2.1
Doorbell Interrupt Operations ......................................................................................................................... 181
19.4.3 Message Signaled Interrupts (MSI).................................................................................................. 181
19.4.3.1
MSI Operation............................................................................................................................................... 182
19.5 NON-TRANSPARENT MODE BOOT UP SEQUENCE ........................................................................................ 183
19.5.1 Using XB_MEM Input to Avoid initial Retry Latency ........................................................................ 183
19.6 NON-TRANSPARENT APPLICATION SYSTEM CONFIGURATION OVERVIEW ...................................................... 185
19.6.1 Memory Allocation Registers Initialization........................................................................................ 185
19.6.2 Basic Initialization Sequence............................................................................................................ 186
19.6.3 Example of Address Setup and Mapping......................................................................................... 187
20 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .................................................................................. 189
21 EEPROM..................................................................................................................................................... 190
21.1 AUTO MODE EEPROM ACCESS ................................................................................................................ 190
21.2 EEPROM MODE AT RESET ....................................................................................................................... 190
21.3 PCI 6254 REV AA ONLY: EEPROM AUTOLOAD IN NON-TRANSPARENT MODE ............................................ 190
21.4 EEPROM DATA STRUCTURE..................................................................................................................... 191
21.4.1 EEPROM Address and Corresponding PCI 6254 Register ............................................................. 192
22 VITAL PRODUCT DATA ............................................................................................................................ 194
23 PCI POWER MANAGEMENT .................................................................................................................... 195
23.1 P_PME# AND S_PME# SIGNALS............................................................................................................... 195
PCI 6254 Data Book v2.1
2003 PLX Technology, Inc. All rights reserved.
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