PDF WJLXT972M Data sheet ( Hoja de datos )

Número de pieza	WJLXT972M
Descripción	Single-Port 10/100 Mbps PHY Transceiver
Fabricantes	Intel
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Hay una vista previa y un enlace de descarga de WJLXT972M (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! .DataShIPenHetteY4lU®T.cLraoXmnTs9c7e2ivMerSingle-Port 10/100DaMtabshpesetThe Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It w provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access w Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported. w Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is powered from a single 3.3V power supply. Applications om■ Combination 10BASE-T/100BASE-TX .cNetwork Interface Cards (NICs) ■ Wireless access points ■ Network printers ■ 10/100 Personal Computer Memory Card International Association (PCMCIA) cards ■ Cable Modems and Set-Top Boxes Product Features t4U■ 3.3V Operation ■ IEEE 802.3-compliant 10BASE-T or e100BASE-TX with integrated filters ■ Auto-negotiation and parallel detection e■ MII interface with extended register capability h■ Robust baseline wander correction ■ Carrier Sense Multiple Access / Collision Detection (CSMA/CD) or full-duplex operation ■ JTAG boundary scan ■ MDIO serial port or hardware pin configurable ■ Integrated, programmable LED drivers ■ 48-pin Low-profile Quad Flat Package taSRESET_L ADDR[1:0] aMDIO MDC .DTX_EN TXD[3:0] TX_CLK wLED/CFG[3:1] wCOL mRX_CLK w oRXD[3:0] .cRX_DV CRS t4URX_ER Management / Mode Select Logic Register Set Clock Generator Power Supply Parallel/Serial Converter Manchester Encoder 10 Scrambler 100 & Encoder Register Set Auto Negotiation OSP Pulse Shaper + TP Driver - TP Out JTAG Collision Detect Clock Generator Carrier Sense Data Valid Error Detect Serial-to- Parallel Converter Manchester 10 Decoder 100 Decoder & Descrambler Media Select OSP Slicer OSP Adaptive EQ with Baseline Wander Cancellation + 100TX - + 10BT - TP In VCC GND REFCLK/XI XO TPOP TPON TDI 5 TDO TMS TCK TRST_L TPIP TPIN B3387-13 .DataSheeDocument Number: 302875-004 wwwRevision Date: February 18, 2005 1 page Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Intel® LXT972M Transceiver Block Diagram ....................................................... 14 Pin Assignments for Intel® LXT972M Transceiver 48-Pin LQFP Package ......... 15 Management Interface Read Frame Structure ................................................... 30 Management Interface Write Frame Structure ................................................... 30 Initialization Sequence for Intel® LXT972M Transceiver ..................................... 33 Link Establishment Overview) ............................................................................. 37 Clocking for 10BASE-T ...................................................................................... 40 Clocking for 100BASE-X .................................................................................... 40 Clocking for Link Down Clock Transition ............................................................ 41 Intel® LXT972M Transceiver Loopback Paths ....................................................43 100BASE-X Frame Format ................................................................................ 44 100BASE-TX Data Path .....................................................................................45 100BASE-TX Reception with No Errors ............................................................. 46 100BASE-TX Reception with Invalid Symbol ..................................................... 46 100BASE-TX Transmission with No Errors ........................................................ 47 100BASE-TX Transmission with Collision .......................................................... 47 Intel® LXT972M Protocol Sublayers.................................................................... 48 LED Pulse Stretching ......................................................................................... 57 Intel® LXT972M Transceiver Typical Twisted-Pair Interface - Switch ................. 61 Intel® LXT972M Transceiver Typical Twisted-Pair Interface - NIC .....................62 Intel® LXT972M Transceiver Typical Media Independent Interface .................... 63 Intel® LXT972M Transceiver 100BASE-TX Receive Timing ............................... 68 Intel® LXT972M Transceiver 100BASE-TX Transmit Timing .............................. 69 Intel® LXT972M Transceiver 10BASE-T Receive Timing ................................... 70 Intel® LXT972M Transceiver 10BASE-T Transmit Timing .................................. 71 Intel® LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing ............... 72 Intel® LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing...................... 73 Intel® LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing .......74 Intel® LXT972M Transceiver Fast Link Pulse Timing .......................................... 74 Intel® LXT972M Transceiver MDIO Input Timing ................................................ 75 Intel® LXT972M Transceiver MDIO Output Timing .............................................75 Intel® LXT972M Transceiver Power-Up Timing .................................................. 76 Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing .......77 PHY Identifier Bit Mapping ................................................................................. 81 Intel® LXT972M Transceiver LQFP Package Specifications............................... 93 Sample LQFP Package - Intel® LXT972A Transceiver ....................................... 94 Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel® LX972A Transceiver. 94 Order Matrix for Intel® LXT972M Transceiver ..................................................... 95 Datasheet Document Number: 302875-004 Revision Date: 27-Oct-2005 5 5 Page Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver er 1.0 Introduction to This Document This document includes information on the Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver (called hereafter the LXT972M Transceiver) 1.1 Document Overview This document includes the following subjects: • Chapter 5.0, “Functional Description” • Chapter 2.0, “Block Diagram for Intel® LXT972M Transceiver” • Chapter 6.0, “Application Information” • Chapter 7.0, “Electrical Specifications” • Chapter 8.0, “Register Definitions - IEEE Base Registers” • Chapter 9.0, “Register Definitions - Product-Specific Registers” • Chapter 3.0, “Pin Assignments for Intel® LXT972M Transceiver” • Chapter 11.0, “Product Ordering Information” 1.2 Related Documents Table 1. Related Documents from Intel Document Title Intel® LXT971A , LXT972A , LXT972M Single-Port 10/100 Mbps PHY Transceivers Specification Update Intel® LXT971A, LXT972A, and LXT972M 3.3V PHY Transceivers Design and Layout Guide - Application Note Magnetic Manufacturers for Networking Product Applications - Application Note Document Number 249354 249016 248991 Document Number: 302875-005 Revision Date: 27-Oct-2005 13 11 Page

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