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AD5601 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5601
Beschreibung (AD5601 - AD5621) SPI Interface / SC70 Package / nanoDAC D/A
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
AD5601 Datasheet, Funktion
om 2.7 V to 5.5 V, <100 µA, 8/10/12BitTM
PreliminatraySTehcehneitc4aUl D.acta nanoDAC D/A, SPAIDIn5t6e0rf1a/cAeD,5S6C1710/PAaDc5k6a2g1eFEATURES
a6-lead SC70 package
.DPower-down to <100 nA @ 3 V
wMicropower operation: max 100 µA @ 5 V
w2.7 V to 5.5 V power supply
wGuaranteed monotonic by design
Power-on-reset to 0 V with brownout detection
m3 power-down functions
oLow power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
.cSYNC interrupt facility
Minimised Zero Code Error
AD5601 Buffered 8-Bit Dac in SC70
UB Version: ±0.5 LSB INL
t4AD5611 Buffered 10-Bit Dac in SC70
B Version: ±0.5 LSB INL, A Version: ±4 LSB INL
AD5621 Buffered 12-Bit Dac in SC70
eB Version: ±1 LSB INL , A Version: ±6 LSB INL
eAPPLICATIONS
hVoltage Level Setting
Portable battery-powered instruments
SDigital gain and offset adjustment
taProgrammable voltage and current sources
Programmable attenuators
aGENERAL DESCRIPTION
.DThe AD5601/AD5611/AD5621, members of the nanoDACTM family, are
single, 8/10/12-bit buffered voltage out DAC that operates from a single 2.7
V to +5.5 V supply consuming <100 µA at 5 V, and comes in a tiny SC70
package. Its on-chip precision output amplifier allows rail-to-rail output
wswing to be achieved. The AD5601/AD5611/AD5621 utilizes a versatile 3-
wire serial interface that operates at clock rates up to 30 MHz and is
wcompatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards.
mThe reference for AD5601/AD5611/AD5621 is derived from the power
w osupply inputs and thus gives the widest dynamic output range. The part
.cincorporates a power-on-reset circuit that ensures the DAC output powers
up to 0 V and remains there until a valid write takes place to the device. The
Upart contains a power-down feature that reduces the current consumption
t4of the device to <100 nA at 3 V and provides software selectable output
eloads while in power-down mode. The part is put into power-down mode
eover the serial interface. The low power consumption of this part in normal
hoperation makes it ideally suited to portable battery operated equipment.
ataSRev. PrB
.DInformation furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
wSpecifications subject to change without notice. No license is granted by implication
wor otherwise under any patent or patent rights of Analog Devices. Trademarks and
wregistered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
Figure 1
RELATED DEVICES
Part Number
Description
AD5641
2.7 V to 5.5 V, <100 µA, 14 Bit nanoDACTM D/A, tiny
SC70 Package
The combination of small package and low power make these devices idea
for level setting requirements such as generating bias or control voltages in
space constrained and power sensitive applications
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD5601 Datasheet, Funktion
AD5601/AD5611/AD5621
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. TA = 25°C, unless otherwise noted
Parameter
Rating
VDD to GND
Digital Input Voltage to GND
VOUT to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
SC70 Package
θJA Thermal Impedance
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
–0.3 V to + 7.0 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–40°C to +125°C
–65°C to +160°C
150°C
332°C/W
120°C/W
215°C
220°C
2.0 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Model
AD5601BKS
AD5611BKS
AD5611AKS
AD5621BKS
AD5621AKS
Temperature
Range
-40OC to 125 OC
-40OC to 125 OC
-40OC to 125 OC
-40OC to 125 OC
-40OC to 125 OC
Description
±0.5 LSB INL
±0.5 LSB INL
±4.0 LSB INL
±1.0 LSB INL
±6.0 LSB INL
Package
Options
KS-6
KS-6
KS-6
KS-6
KS-6
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 6 of 17

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AD5601 pdf, datenblatt
AD5601/AD5611/AD5621
Preliminary Technical Data
GENERAL DESCRIPTION
D/A SECTION
The AD5601/AD5611/AD5621 DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 22 shows a block
diagram of the DAC architecture.
VDD
DAC REGISTER
REF (+)
RESISTOR
NETWORK
REF (ٛ–)
GND
VOUT
OUTPUT
AMPLIFIER
Figure 22. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
where D = decimal equivalent of the binary code that is loaded
to the DAC register.
RESISTOR STRING
The resistor string section is shown in Figure 21. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 9 and Figure 10. The slew rate is 0.5 V/µs
with a half-scale settling time of 8 µs with the output unloaded.
DB15 (MSB)
SERIAL INTERFACE
The AD5601/AD5611/AD5621 have a three-wire serial
interface (SYNC, SCLK and DIN), which is compatible with SPI,
QSPI and MICROWIRE interface standards as well as most
DSPs. See Figure 2 for a timing diagram of a typical write
sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5601/AD5611/AD5621compatible
with high speed DSPs. On the 16th falling clock edge, the last
data bit is clocked in and the programmed function is executed
(i.e., a change in DAC register contents and/or a change in the
mode of operation). At this stage, the SYNC line may be kept
low or be brought high. In either case, it must be brought high
for a minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when VIN = 1.8 V than it
does when VIN = 0.8 V, SYNC should be idled low between write
sequences for even lower power operation of the part, as
mentioned above; however, it must be brought high again just
before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 23). The first
two bits are control bits that control which mode of operation
the part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next sixteen bits
are the data bits. These are transferred to the DAC register on
the 16th falling edge of SCLK.
DBO (LSB)
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
0 0 NORMAL OPERATION
0 1 1 kTO GND
1 0 100 kTO GND POWER-DOWN MODES
1 1 THREE-STATE
Figure 23. Input Register Contents
Rev. PrB | Page 12 of 17

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