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PDF PLL205-03 Data sheet ( Hoja de datos )
| Número de pieza | PLL205-03 | |
| Descripción | Motherboard Clock Generator | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL205-03 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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.com PLL205-03Motherboard Clock Generator for AMD - K7
et4UFEATURES
She• Generates all clock frequencies for VIA K7 chip
tasets requiring multiple CPU clocks and high
aspeed SDRAM buffers.
.D• Support one pair of differential CPU clocks, one
3.3V push-pull CPU clock, 6 PCI and 13 high-
wspeed SDRAM buffers for 3-DIMM applications.
ww• One 24_48MHz clock and one 48MHz clock.
m• Two14.318MHz reference clocks.
• Power management control to stop CPU, and
oPower down Mode from I2C programming.
.c• Support 2-wire I2C serial bus interface with built-
in Vendor ID, Device ID and Revision ID.
• Single byte micro-step linear Frequency Progra-
Umming via I2C with Glitch free smooth switching.
t4• Enhanced CPU and SDRAM output Drive
selectable by I2C.
e• Spread Spectrum ±0.25% center spread, 0 to
-0.5% downspread.
e• 50% duty cycle with low jitter.
h• Available in 300 mil 48 pin SSOP.
SBLOCK DIAGRAM
taXIN
aXOUT
XTAL
OSC
.DSDATA
SCLK
wFS (0:3)*
ww .comPD
I2C
Logic
PLL1
SST
Control
Logic
eet4UPLL2
÷2
ataShSDRAMIN
VDD1
REF(0:1)
CPUT1
CPUT0
CPUC0
VDD2
PCI(0:4)
PCI5
VDD4
48Mhz
24_48Mhz
VDD3
SDRAM(0:11)
SDRAM12
PIN CONFIGURATION
VDD0
REF0//CPU_STOP#^
GND
XIN
XOUT
VDD1
PCI5/MODE*^
PCI0/FS3*^
GND
PCI1/SEL24_48*^
PCI2
PCI3
PCI4
VDD2
SDRAMIN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2*^
47 GND
46 CPUT1
45 GND
44 CPUC0
43 CPUT0
42 VDD3
41 PD#^
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDD3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDD3
29 SDRAM6
28 SDRAM7
27 VDD4
26 48MHz/FS0*^
25 24_48MHz/FS1*^
Note: ^: Pull up, #: Active Low
*: Bi-directional latched at power-up
I/O MODE CONFIGURATION
MODE (Pin 7)
1 (OUTPUT)
0 (INPUT)
PIN 2
REF0
CPU_STOP
POWER GROUP
• VDD0: PLL CORE
• VDD1: REF(0:1), XIN, XOUT
• VDD2: PCI(0:5)
• VDD3: SDRAM(0:12)
• VDD4: 48MHz, 24_48MHz
KEY SPECIFICATIONS
• CPU Cycle to Cycle jitter: 250ps.
• PCI to PCI output skew: 500ps.
• CPU to CPU output skew: ±175ps
• SDRAM to SDRAM output skew: 250ps.
• CPU to PCI skew (CPU leads): 0 ~ 3 ns.
www.D47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/23/00 Page 1
1 page  
PLL205-03
Motherboard Clock Generator for AMD - K7
BYTE 1: CPU Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
Bit 7 -
17,18,20,21,
Bit 6 28,29,31,32,
34,35,37,38
Bit 5 46
Bit 4 43,44
Bit 3 40
Bit 2 -
Bit 1 43,44
Bit 0 46
1 Reserved
1 High Strength SDRAM Select ( 1=Normal, 0= Enhanced by 25% )
1 Enhanced CPUT1 Drive Select ( 1=Normal, 0=Enhanced by 25% )
1
Enhanced CPUT0, CPUC0 Drive Select
(1=Normal, 0=Enhanced by 25%)
1 SDRAM12 ( Active/Inactive )
1 Reserved
1 CPUT0, CPUC0 ( Active/Inactive )
1 CPUT1 ( Active/Inactive )
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
Bit 7 -
Bit 6 7
Bit 5 -
Bit 4 13
Bit 3 12
Bit 2 11
Bit 1 10
Bit 0 8
1 Reserved
1 PCI5 ( Active/Inactive )
1 Reserved
1 PCI4 ( Active/Inactive )
1 PCI3 ( Active/Inactive )
1 PCI2 ( Active/Inactive )
1 PCI1 ( Active/Inactive )
1 PCI0 ( Active/Inactive )
4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/23/00 Page 5
5 Page 
PLL205-03
Motherboard Clock Generator for AMD - K7
2. Output Buffer Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V±5%, and ambient temperature range TA= 0°C to 70°C
PARAMETERS SYMBOL
OUTPUTS
CONDITIONS
Output Rise time
Output Fall time
Duty Cycle
CPUT1
CPU (Open Drain)
TOR REF(0:1)
PCI(0:5)
24_48MHz, 48MHz
CPUT1
CPU (Open Drain)
TOF REF(0:1)
PCI(0:5)
24_48MHz, 48MHz
REF(0:1),CPU,
DT PCI(0:5)
24_48MHz, 48MHz
Measured @ 0.3V ~ 1.2V,
CL=20pf, 3.3V±5%
Measured @ 0.3V ~ 1.2V,
CL=20pf, 3.3V±5%
Measured @ 0.4V ~ 2.4V,
CL=20pf, 3.3V±5%
Measured @ 0.4V ~ 2.4V,
CL=30pf, 3.3V±5%
Measured @ 0.4V ~ 2.4V,
CL=20pf, 3.3V±5%
Measured @ 0.3V ~ 1.2V,
CL=20pf, 3.3V±5%
Measured @ 1.2V ~ 0.3V,
CL=20pf, 3.3V±5%
Measured @ 2.4V ~ 0.4V,
CL=20pf, 3.3V±5%
Measured @ 2.4V ~ 0.4V,
CL=30pf, 3.3V±5%
Measured @ 2.4V ~ 0.4V,
CL=20pf, 3.3V±5%
VT = 50%
VT = 1.5V
CPUT1 to CPUT0
Clock Skew
TSKEW
PCI to PCI
CPU to PCI
VT = 50%
CPU to AGP
Output
Impedance
CPUT1
CPU
PCI(0:5)
Z0
REF(0:1)
REF1
24_48MHz, 48MHz
VO = VX
VDD=3.3V±5%
MIN.
45
0
-500
TYP.
30
50
30
40
40
40
MAX. UNITS
2
0.9
4 ns
2
4
2
0.9
4 ns
2
4
55 %
200
ps
200
3
ns
500
Ohm
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/23/00 Page 11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PLL205-03.PDF ] | |
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