|
|
PDF PLL205-16 Data sheet ( Hoja de datos )
| Número de pieza | PLL205-16 | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PLL205-16 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
om PLL205-16Preliminary
.cProgrammable Clock Generator for VIA KT-266 Chipset
t4UFEATURES
ee• Generates all clock frequencies for VIA KT266
hchipset.
taS• Support one pair of differential CPU clocks, one
apair of differential push-pull CPU clocks, 3 AGP
.Dand 10 PCI.
w• Enhanced PCI Output Drive selectable by I2C.
w• One 48MHz clock and 24_48MHz clock via I2C.
w• Three 14.318MHz reference clocks.
m• Power management control to stop CPU, PCI,
REF, 24_48MHz, 48MHz and AGP clocks.
o• Supports 2-wire I2C serial bus interface with
.creadback.
• Single byte micro-step linear Frequency
Programming via I2C with glitch free smooth
Uswitching.
t4• Built-in programmable watchdog timer up to 63
seconds with 1-second interval. It will generate a
elow reset output when timer expired.
• Spread Spectrum ±0.25% center, ±0.5% center,
e±0.75% center, and 0 to -0.5% downspread.
h• 50% duty cycle with low jitter.
S• Available in 300 mil 48 Pin SSOP.
PIN CONFIGURATION
VDD1
GND
XIN
XOUT
VDD2
48MHz/FS2*^
24_48MHz/FS3* ^
GND
FS4*^/PCI_F
SEL24_48#^/PCI0
PCI1
GND
PCI2
PCI3
VDD3
PCI4
PCI5
PCI6
GND
PCI7
PCI8
PCI9_E/SELPCI9_E*^
VDD3
WDRESET#^
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF0/FS0*^
47 REF1/FS1*^
46 REF_F
45 N/C
44 AGP_STOP#^
43 GND
42 CPUT0
41 CPUC0
40 VDDL1
39 CPUT_CS
38 CPUC_CS
37 GND
36 CPU_STOP#^
35 PCI_STOP#^
34 PD#^
33 VDDL2
32 GND
31 SDATA
30 SCLK
29 GND
28 AGP2
27 AGP1
26 AGP0
25 VDD4
Note: ^: 100k internal Pull up v: 100k internal Pull down
#: Active low *: Bi-directional up latched at power-up
taBLOCK DIAGRAM
aXIN
XOUT
XTAL
OSC
.DFS (0:4)*
www mPLL1
oSST
Control
Logic
t4U.cPD
ataSheeSDATA
.DSCLK
PLL2
I2C
Logic
÷2
Watch
Dog
VDD1
REF(0:1)
REF_F
CPUT0
CPUC0
VDDL1
CPUT_CS
CPUC_CS
VDD4
AGP (0:2)
VDD3
PCI (0:8)
PCI9_E
VDD2
48MHz
24_48MHz
WDRESET#
POWER GROUP
• VDD1: REF(0:1), REF_F, XIN, XOUT
• VDD2: 48MHz or 24_48MHz
• VDD3: PCI(0:8), PCI9_E
• VDD4: AGP(0:2)
• VDDL1: CPUT0, CPUC0, CPUT_CS, CPUC_CS
• VDDL2: PLL Core
KEY SPECIFICATIONS
• CPU Cycle to Cycle jitter: 250ps.
• PCI Cycle to Cycle jitter: 500ps.
• PCI to PCI skew: 500ps.
• CPU to CPU skew: 175ps.
• AGP to AGP skew: 250ps.
www47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/21/01 Page 1
1 page  
Preliminary PLL205-16
Programmable Clock Generator for VIA KT-266 Chipset
FREQUENCY (MHz) SELECTION TABLE BY GROUP TIMING
Divider Ratio
(CPU:AGP)
FS4
FS3
FS2
FS1
FS0
A ( 1: 1 )
11011
11110
01111
01110
B (1.5 : 1 )
0
1
1
1
1
0
0
1
1
0
01100
01011
01010
11001
01001
01000
11111
00111
00110
B(2:1)
11000
00101
00100
00011
10111
00010
00001
00000
11101
C ( 2.5 : 1 )
1
1
0
0
1
1
1
0
0
1
10100
11100
10011
D(3:1)
10010
10001
10000
CPU
66.6
100
102
105
108
110
113
115
117
120
122
124
133.33
136
138
140
142
144
147
150
152
154
156
166.6
170
180
190
200
200
210
220
233.3
AGP
66.6
66.67
68
70
72
73.3
75.3
76.7
78
60
61
62
66.67
68
69
70
71
72
73.5
75
76
77
78
66.64
68
72
76
66.6
66.6
70
73.3
77.78
PCI
33.3
33.33
34
35
36
36.67
37.7
38.3
39
30
30.5
31
33.33
34
34.5
35
35.5
36
36.8
37.5
38
38.5
39
33.32
34
36
38
33.3
33.3
35
36.6
38.88
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/21/01 Page 5
5 Page 
Preliminary PLL205-16
Programmable Clock Generator for VIA KT-266 Chipset
8. BYTE 7: Reserved Register (For external DDR buffer)
Bit
Pin#
Default
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 -
1 Reserved
Bit 3 -
1 Reserved
Bit 2 -
1 Reserved
Bit 1 -
1 Reserved
Bit 0 -
1 Reserved
Description
9. BYTE 8: Watchdog Timer / Revision ID and Vendor ID Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7 -
0 Watchdog Timer Enable Bit. 1=Enable, 0=Disable
Bit 6 -
0 Revision ID Bit 2*
Bit 5 -
Bit 4 -
0 Watchdog Time Interval Bit 5 (MSB)
0 Watchdog Time Interval Bit 4
Revision ID Bit 1*
Revision ID Bit 0*
Bit 3 -
Bit 2 -
0 Watchdog Time Interval Bit 3
0 Watchdog Time Interval Bit 2
Vendor ID Bit 3*
Vendor ID Bit 2*
Bit 1 -
Bit 0 -
1 Watchdog Time Interval Bit 1
1 Watchdog Time Interval Bit 0 (LSB)
Vendor ID Bit 1*
Vendor ID Bit 0*
Note: *: Default value at power-up. Don’t write into this register, writing into this register can cause malfunction.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/21/01 Page 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet PLL205-16.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PLL205-11 | Motherboard Clock Generator | PhaseLink |
| PLL205-13 | Motherboard Clock Generator | PhaseLink |
| PLL205-14 | Programmable Clock Generator | PhaseLink |
| PLL205-16 | Programmable Clock Generator | PhaseLink |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |