RD48Fxxxx Datasheet PDF - Intel
| Part Number | RD48Fxxxx | |
| Description | 768Mbit LVQ Family | |
| Manufacturers | Intel | |
| Logo |  |
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There is a preview and RD48Fxxxx download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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hSIenyettes4tleSmtra(LtaVF1l8a/sLhV30WSirCeSlePs)s Memory768-Mbit LVQ Family with Asynchronous Static RAM
.DataS Product Features
Datasheet
ww ■ Device Architecture
■ xRAM Performance
w — Code and data segment: 128- and 256-
mMbit density; PSRAM: 32- and 64-Mbit
density; SRAM: 8 Mbit density.
— PSRAM at 1.8 V I/O : 85 ns initial
access, 30 ns async page reads; 65 ns
initial access, 18 ns async page.
o—Top or bottom parameter configuration.
.c—Asymmetrical blocking structure.
— 16-KWord parameter blocks (Top or
Bottom); 64-K Word main blocks.
U—Zero-latency block locking.
t4—Absolute write protection with block
lock down using F-WP#.
e■ Device Voltage
— Core: VCC = 1.8 V (typ).
e—I/O: VCCQ = 1.8 V or 3.0 V (typ).
h■ Device Concurrent Operations (3 Dies)
— Buffered EFP: 600 KB per second.
S—Erase Performance: 384 KB per second
(main blocks).
ta■ Device Packaging
— 88 balls (8 x 10 active ball matrix).
a—Area: 8 x 10 mm or 8 x 11 mm.
— Height: 1.0 mm to 1.4 mm.
.D■ Quality and Reliability
— Extended Temp: –25 °C to +85 °C.
— SRAM at 1.8 or 3.0 V I/O: 70 ns initial
access.
■ Flash Performance
— Code Segment at 1.8 V I/O: 85 ns initial
access; 25 ns async page read; 14 ns
sync reads (tCHQV); 54 MHz CLK.
— Data Segment at 1.8 V I/O: 170 ns initial
access; 55 ns async page read.
■ Flash Architecture
— Hardware Read-While-Write/Erase.
— 8-Mbit or 16-Mbit Multi-Partition.
— 2-Kbit One-Time Programmable (OTP)
Protection Register.
— Software Read-While-Write/Erase.
— Single Full-Die Partition size.
■ Flash Software
— Intel£ FDI, Intel£ PSM, and Intel£
VFM.
— Common Flash Interface (CFI).
— Basic/Extended Command Set.
w—Minimum 100 K flash block erase cycle.
The Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 768-Mbit LVQ Family
wwith Asynchronous Static RAM device offers a high performance code and large embedded data
msegment plus RAM combination in a common package with electrical QUAD+ ballout on 0.13
w oµm ETOX™ VIII flash technology. The code segment flash die features 1.8 V low-power
.coperations with flexible, multi-partition, dual operation Read-While-Write / Read-While-Erase,
asynchronous and synchronous burst reads at 54 MHz. The data segment flash die features 1.8 V
Ulow-power operations optimized for cost sensitive asynchronous data applications. This device
t4integrates up to three flash dies, two PSRAM dies, and one SRAM die in a low-profile package
ecompatible with other SCSP families using the QUAD+ ballout package.
heNotice: This document contains information on new products in production. The specifications
Sare subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
.Data 253852-002
www December 2003
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1.0
1.1
768-Mbit LVQ Family with Asynchronous Static RAM
Introduction
This document provides information about the Intel StrataFlash® Wireless Memory System (LV18/
LV30 SCSP); 768-Mbit LVQ Family with Asynchronous Static RAM device, including
information on the features, characteristics, operations, and specifications for:
• Code and data segment flash dies
• SRAM and PSRAM dies
The intent of this document is to provide information where this 768-Mbit LVQ Family with
Asynchronous Static RAM Stacked Chip Scale Package (SCSP) device differs from the Intel
StrataFlash® Wireless Memory System (LV18/LV30 SCSP); 1024-Mbit LV Family device. Refer
to the latest revision of the Intel StrataFlash® Wireless Memory System (LV18/LV30 SCSP; 1024-
Mbit LV Family Datasheet (order number 253854) for flash product details not included in this
document.
Nomenclature
0x
0b
Byte
CFI
DU
ETOX
k (noun)
Kb
KB
Kword
M (noun)
Mb
MB
OTP
RCR
RFU
SCSP
SR
SRD
Word
1.8 V Core
1.8 V I/O
Asserted
Deasserted
High-Z
Low-Z
Hexadecimal prefix
Binary prefix
8 bits
Common Flash Interface
Don’t Use
EPROM Tunnel Oxide
1 thousand
1024 bits
1024 bytes
1024 words
1 million
1,048,576 bits
1,048,576 bytes
One-time Programmable
Read Configuration Register
Reserved for Future Use
Stacked Chip Scale Package
Status Register
Status Register Data
16 bits
range of 1.7 V – 1.95 V
range of 1.7 V – 1.95 V
Signal with logical voltage level VIL, or enabled
Signal with logical voltage level VIH, or disabled
Tri-stated or High Impedance
Driven
Datasheet
5
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| Information | Total 30 Pages | |
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