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ADSP-2192M Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2192M
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-2192M Datasheet, Funktion
ataSheet4U.com DSP MADicSrPo-c2o1m9p2uMterADSP-2192M DUAL CORE DSP FEATURES
320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package
awith PCI, USB, Sub-ISA, and CardBus Interfaces
.D3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface
wwith Bus Mastering over Four DMA Channels with
Scatter-Gather Support
w Integrated USB 1.1 Compliant Interface
w Sub-ISA Interface
mAC’97 Revision 2.1 Compliant Interface for External
Audio, Modem, and Handset Codecs with DMA
oCapability
Dual ADSP-219x Core Processors (P0 and P1) on Each
.cADSP-2192M DSP Chip
132K Words of Memory Includes 4K ؋ 16-Bit Shared
Data Memory
80K Words of On-Chip RAM on P0, Configured as
64K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
48K Words of On-Chip RAM on P1, Configured as
32K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
4K Words of Additional On-Chip RAM Shared by Both
Cores, Configured as 4K Words On-Chip 16-Bit RAM
Flexible Power Management with Selectable Power-
Down and Idle Modes
Programmable PLL Supports Frequency Multiplication,
Enabling Full Speed Operation from Low Speed
Input Clocks
2.5 V Internal Operation Supports 3.3 V/5.0 V
Compliant I/O
heet4UADSP-219x
SDSP CORE
FUNCTIONAL BLOCK DIAGRAM
P0
MEMORY
16K؋24 PM
64K؋16 DM
BOOT ROM
ADDR DATA
SHARED
MEMORY
4K؋16 DM
ADDR DATA
P1
MEMORY
16K؋24 PM
32K؋16 DM
BOOT ROM
ADDR DATA
ADSP-219x
DSP CORE
ta(SEE FIGURE 1
ON PAGE 3)
.DaCORE
INTERFACE
PROCESSOR P0
ADDR DATA
P0 DMA
w CONTROLLER
w FIFOS
ADDR DATA
SHARED DSP
I/O MAPPED
REGISTERS
(SEE FIGURE 1
ON PAGE 3)
CORE
INTERFACE
ADDR DATA
PROCESSOR P1
P1 DMA
CONTROLLER
FIFOS
w t4U.comGP I/O PINS
(AND
eOPTIONAL
SERIAL
eEEPROM)
SERIAL PORT
AC'97
COMPLIANT
HOST PORT
PCI 2.2
OR
USB 1.1
JTAG
EMULATION
PORT
ataShREV. 0
.DInformation furnished by Analog Devices is believed to be accurate and
wreliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
wmay result from its use. No license is granted by implication or otherwise
wunder any patent or patent rights of Analog Devices. Trademarks and
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
registered trademarks are the property of their respective companies.
Fax:781/326-8703
© 2002 Analog Devices, Inc. All rights reserved.






ADSP-2192M Datasheet, Funktion
ADSP-2192M
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
Table 3. Interrupt Control (ICNTL) Register Bits
Bit
0–3
4
5
6
7
8–9
10
11
12
13–15
Description
Reserved
Interrupt nesting enable
Global interrupt enable
Reserved
MAC biased rounding enable
Reserved
PC stack interrupt enable
Loop stack interrupt enable
Low power idle enable
Reserved
The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically main-
tained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is eight levels deep, and the status stack is 16 levels deep. To
prevent stack overflow, the PC stack can generate a stack level
interrupt if the PC stack falls below three locations full or rises
above 28 locations full.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.
DMA Controller
The ADSP-2192M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2192M’s internal memory and any of its DMA-capable
peripherals. DMA transfers can also be accomplished between
any of the DMA-capable peripherals. DMA-capable peripherals
include the PCI and AC’97 ports. Each individual DMA-capable
peripheral has a dedicated DMA channel. DMA sequences do
not contend for bus access with the DSP core; instead, DMAs
“steal” cycles to access memory. All DMA transfers use the
Program Memory (PMA/PMD) buses shown in the Functional
Block Diagram on Page 1.
External Interfaces
Several different interfaces are supported on the ADSP-2192M.
These include both internal and external interfaces. The three
separate PCI configuration spaces are programmable to set up
the device in various Plug-and-Play configurations.
The ADSP-2192M provides the following types of external inter-
faces: PCI, USB, Sub-ISA, CardBus, AC’97, and serial
EEPROM. The following sections discuss those interfaces.
PCI 2.2 Host Interface
The ADSP-2192M includes a 33 MHz, 32-bit bus master PCI
interface that is compliant with revision 2.2 of the PCI specifica-
tion. This interface supports the high data rates.
USB 1.1 Host Interface
The ADSP-2192M USB interface enables the host system to
configure and attach a single device with multiple interfaces and
various endpoint configurations. The advantages of this design
include:
Programmable descriptors and class-specific command
interpreter.
An on-chip 8052-compatible MCU allows the user to soft
download different configurations and support standard
or class-specific commands.
Total of eight user-defined endpoints provided.
Endpoints can be configured as either BULK, ISO, or
INT, and the endpoints can be grouped and assigned to
any interface.
Sub-ISA Interface
In systems that combine the ADSP-2192M chip with other
devices on a single PCI interface, the ADSP-2192M Sub-ISA
mode is used to provide a simpler interface that bypasses the
ADSP-2192M’s PCI interface. In this mode the Combo Master
assumes all responsibility for interfacing the function to the PCI
bus, including provision of Configuration Space registers for the
ADSP-2192M system as a separate PnP function. In Sub-ISA
Mode the PCI Pins are reconfigured for ISA operation.
CardBus Interface
The CardBus standard provides higher levels of performance
than the 16-bit PC Card standard. For example, 32-bit CardBus
cards are able to take advantage of internal bus speeds that can
be as much as four to six times faster than 16-bit PC Cards. This
design provides for a compact, rugged card that can be completely
inserted within its host computer without any external cabling.
Because CardBus performance attains the same high level as the
host platform’s internal (PCI) system bus, it is an excellent way
to add high speed communications to the notebook form factor.
In addition, CardBus PC Cards operate at a power-saving
3.3 volts, extending battery life in most configurations.
This new 32-bit CardBus technology provides up to 132M bytes
per second of bandwidth. This performance makes CardBus an
ideal vehicle to meet the demands of high throughput communi-
cations such as ADSL.
–6– REV. 0

6 Page









ADSP-2192M pdf, datenblatt
ADSP-2192M
Table 8. 24-Bit PCI DSP Memory Map (BAR2 Mode)1 (continued)
Block
Byte3
Byte2
Byte1
Byte0
DSP P0 Program ROM
Block
UNUSED
UNUSED
...
UNUSED
D[23:16]
D[23:16]
...
D[23:16]
D[15:8]
D[15:8]
...
D[15:8]
D[7:0]
D[7:0]
...
D[7:0]
Reserved Space
RESERVED
...
RESERVED
RESERVED
...
RESERVED
RESERVED
...
RESERVED
RESERVED
...
RESERVED
DSP P1 Data RAM
Block 0
UNUSED
UNUSED
...
UNUSED
D[15:8]
D[15:8]
...
D[15:8]
D[7:0]
D[7:0]
...
D[7:0]
UNUSED
UNUSED
...
UNUSED
DSP P1 Data RAM
Block 1
Reserved Space
UNUSED
UNUSED
...
UNUSED
UNUSED
UNUSED
...
UNUSED
D[15:8]
D[15:8]
...
D[15:8]
D[15:8]
D[15:8]
...
D[15:8]
D[7:0]
D[7:0]
...
D[7:0]
D[7:0]
D[7:0]
...
D[7:0]
UNUSED
UNUSED
...
UNUSED
UNUSED
UNUSED
...
UNUSED
DSP P1 Program RAM
Block
UNUSED
UNUSED
...
UNUSED
D[23:16]
D[23:16]
...
D[23:16]
D[15:8]
D[15:8]
...
D[15:8]
D[7:0]
D[7:0]
...
D[7:0]
DSP P1 Program ROM
Block
UNUSED
UNUSED
...
UNUSED
D[23:16]
D[23:16]
...
D[23:16]
D[15:8]
D[15:8]
...
D[15:8]
D[7:0]
D[7:0]
...
D[7:0]
Reserved Space
RESERVED
...
RESERVED
RESERVED
...
RESERVED
RESERVED
...
RESERVED
RESERVED
...
RESERVED
1The “. . .” entries in this table indicate the continuation of the pattern shown in the first rows of each section.
16-Bit PCI DSP Memory Map (BAR3)
The complete PCI address footprint for the ADSP-2192M DSP
Memory Spaces in 16-bit (BAR3) Mode is shown in Table 9.
Table 9. 16-Bit PCI DSP Memory Map (BAR3 Mode)1
Block
DSP P0 Data RAM
Block 0
DSP P0 Data RAM
Block 1
DSP P0 Data RAM
Block 2
Byte3
D[15:8]
D[15:8]
...
D[15:8]
D[15:8]
D[15:8]
...
D[15:8]
D[15:8]
D[15:8]
...
D[15:8]
Byte2
D[7:0]
D[7:0]
...
D[7:0]
D[7:0]
D[7:0]
...
D[7:0]
D[7:0]
D[7:0]
...
D[7:0]
Byte1
D[15:8]
D[15:8]
...
D[15:8]
D[15:8]
D[15:8]
...
D[15:8]
D[15:8]
D[15:8]
...
D[15:8]
Byte0
D[7:0]
D[7:0]
...
D[7:0]
D[7:0]
D[7:0]
...
D[7:0]
D[7:0]
D[7:0]
...
D[7:0]
Offset
0x0005 0000
0x0005 0004
...
0x0005 3FFC
0x0005 4000
...
0x0007 FFFC
0x0008 0000
0x0008 0004
...
0x0008 FFFC
0x0009 0000
0x0009 0004
...
0x0009 FFFC
0x000A 0000
0x000A 0004
...
0x000B FFFC
0x000C 0000
0x000C 0004
...
0x000C FFFC
0x000D 0000
0x000D 0004
...
0x000D 3FFC
0x000D 4000
...
0x000F FFFC
Offset
0x0000 0000
0x0000 0004
...
0x0000 7FFC
0x0000 8000
0x0000 8004
...
0x0000 FFFC
0x0001 0000
0x0001 0004
...
0x0001 7FFC
–12–
REV. 0

12 Page





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