Datenblatt-pdf.com


ADSP21990 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP21990
Beschreibung Mixed Signal DSP Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP21990 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
aPrelitamSinheaeryt4TUe.ccohmnical Data Mixed Signal DASDPSPC-o2n1t9r9o0llerMIXED SIGNAL DSP CONTROLLER FEATURES
ADSP-219x, 16-bit, Fixed Point DSP Core with up to 160
aMIPS sustained performance
.D8K Words of On chip RAM, Configured as 4K Words On
wchip 24-bit Program RAM and 4K Words On chip 16-bit
Data RAM
w External Memory Interface
w Dedicated Memory DMA Controller for Data/Instruction
mTransfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
oCircuitry Enables Full speed Operation from Low
speed Input Clocks
.cIEEE JTAG Standard 1149.1 Test Access Port Supports
On chip Emulation and System Debugging
8-Channel, 20 MSPS, 14-bit Analog to Digital Converter
USystem
Three Phase 16-bit Center Based PWM Generation Unit
with 12.5 ns resolution
Dedicated 32-bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-bit Auxiliary PWM Outputs
16 General Purpose Flag I/O Pins
Three Programmable 32-bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0V Voltage Reference
Integrated Power-On-Reset (POR) Generator
t4FUNCTIONAL BLOCK DIAGRAM
SheeJTAG
TEST &
taEMULATION
CLOCK
GENERATOR / PLL
160 MHZ
ADSP-219X
DSP
aI/O
BUS
w.DI/O REGISTERS
4K X 24
PM RAM
(BLOCK 0)
4K X 16
DMRAM
(BLOCK 1)
4K X 24
PMROM
(BLOCK 2)
PM ADDRESS/DATA
DM ADDRESS/DATA
EXTERNAL
MEMORY
INTERFACE
(EMI)
ADDRESS
DATA
CONTROL
MEMORY DMA
CONTROLLER
ww omTIMER0
ADC CONTROL
PWM
ENCODER AUXILIARY
INTERRUPT
.cGENERATION INTERFACE
PWM
TIMER 1
FLAG
SPI
SPORT
WATCHDOG CONTROLLER
UUNIT
UNIT
(AND EET)
UNIT
TIMER 2
I/O
TIMER
(ICNTL)
PIPELINE
t4FLASH ADC
heePOR
VREF
ataSREV. PrA
w.DThis information applies to a product under development. Its characteristics and specifi- One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
cations are subject to change without notice. Analog Devices assumes no obligation Tel:781/329-4700
www.analog.com
wwregarding future manufacturing unless otherwise agreed to in writing.
Fax:781/326-8703
©Analog Devices,Inc., 2002






ADSP21990 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
ADSP-21990
For current information contact Analog Devices at (781) 937-1799
February 2002
addresses (IO pages 32 to 255) are available for external
peripheral devices. External I/O pages have their own select
pin (IOMS). The DSP instruction set provides instructions
for accessing I/O space.
0x00::0x000
0x1F::0x3FF
0x20::0x000
On-Chip
Peripherals
16-bits
Pages 0 to 31
1024 words/page
2 Peripherals/page
Off-Chip
Peripherals
16-bits
0xFF::0x3FF
Pages 32 to 255
1024 words/page
Figure 3. ADSP-21990 I/O Memory Map
Boot Memory Space
Boot memory space consists of one off chip bank with 254
pages. The BMS memory bank pin selects boot memory
space. Both the ADSP-219x core and DMA capable periph-
erals can access the DSP’s off chip boot memory space. After
reset, the DSP always starts executing instructions from the
on chip boot ROM.
0x010000
Off-Chip
Boot Memory
16-bits
0xFE0000
Pages 1 to 254
64 kWords/Page
Figure 4. ADSP-21990 Boot Memory Map
Bus Request and Bus Grant
The ADSP-21990 can relinquish control of the data and
address buses to an external device. When the external
device requires access to the bus, it asserts the bus request
(BR) signal. The (BR) signal is arbitrated with core and
peripheral requests. External Bus requests have the lowest
priority. If no other internal request is pending, the external
bus request will be granted. Due to synchronizer and arbi-
tration delays, bus grants will be provided with a minimum
of three peripheral clock delays. The ADSP-21990 will
respond to the bus grant by:
Three stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.
Asserting the bus grant (BG) signal.
The ADSP-21990 will halt program execution if the bus is
granted to an external device and an instruction fetch or
data read/write request is made to external general purpose
or peripheral memory spaces. If an instruction requires two
external memory read accesses, the bus will not be granted
between the two accesses. If an instruction requires an
external memory read and an external memory write access,
the bus may be granted between the two accesses. The
external memory interface can be configured so that the
core will have exclusive use of the interface. DMA and Bus
Requests will be granted. When the external device releases
BR, the DSP releases BG and continues program execution
from the point at which it stopped.
The bus request feature operates at all times, even while the
DSP is booting and RESET is active.
The ADSP-21990 asserts the BGH pin when it is ready to
start another external port access, but is held off because
the bus was previously granted. This mechanism can be
extended to define more complex arbitration protocols for
implementing more elaborate multimaster systems.
DMA Controller
The ADSP-21990 has a DMA controller that supports
automated data transfers with minimal overhead for the
DSP core. Cycle stealing DMA transfers can occur between
the ADSP-21990’s internal memory and any of its DMA
capable peripherals. Additionally, DMA transfers can be
accomplished between any of the DMA capable peripherals
and external devices connected to the external memory
interface. DMA capable peripherals include the SPORT
and SPI ports, and ADC Control module. Each individual
DMA capable peripheral has a dedicated DMA channel. To
describe each DMA sequence, the DMA controller uses a
set of parameters—called a DMA descriptor. When succes-
sive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one
DMA sequence auto initiates and starts the next sequence.
DMA sequences do not contend for bus access with the DSP
core, instead DMAs “steal” cycles to access memory.
6 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA

6 Page









ADSP21990 pdf, datenblatt
PRELIMINARY TECHNICAL DATA
ADSP-21990
For current information contact Analog Devices at (781) 937-1799
February 2002
For each peripheral interrupt source, there is a unique 4-bit
code that allows the user to assign the particular peripheral
interrupt to any one of the 12 user assignable interrupts of
the embedded ADSP-219x core. Therefore, the peripheral
interrupt controller of the ADSP-21990 contains 8, 16-bit
Interrupt Priority Registers (Interrupt Priority Register 0
(IPR0) to Interrupt Priority Register 7 (IPR7)).
Each Interrupt Priority Register contains a four 4-bit codes;
one specifically assigned to each peripheral interrupt. The
user may write a value between 0x0 and 0xB to each 4-bit
location in order to effectively connect the particular
interrupt source to the corresponding user assignable
interrupt of the ADSP-219x core.
Writing a value of 0x0 connects the peripheral interrupt to
the USR0 user assignable interrupt of the ADSP-219x core
while writing a value of 0xB connects the peripheral
interrupt to the USR11 user assignable interrupt. The core
interrupt USR0 is the highest priority user interrupt, while
USR11 is the lowest priority. Writing a value between 0xC
and 0xF effectively disables the peripheral interrupt by not
connecting it to any ADSP-219x core interrupt input. The
user may assign more than one peripheral interrupt to any
given ADSP-219x core interrupt. In that case, the onus is
on the user software in the interrupt vector table to
determine the exact interrupt source through reading status
bits etc.
This scheme permits the user to assign the number of
specific interrupts that are unique to their application to the
interrupt scheme of the ADSP-219x core. The user can then
use the existing interrupt priority control scheme to dynam-
ically control the priorities of the 12 core interrupts.
Low Power Operation
The ADSP-21990 has four low power options that signifi-
cantly reduce the power dissipation when the device
operates under standby conditions. To enter any of these
modes, the DSP executes an IDLE instruction. The
ADSP-21990 uses the configuration of the PD, STCK, and
STALL bits in the PLLCTL register to select between the
low power modes as the DSP executes the IDLE instruction.
Depending on the mode, an IDLE shuts off clocks to
different parts of the DSP in the different modes. The low
power modes are:
Idle
Power Down Core
Power Down Core/Peripherals
Power Down All
Idle Mode
When the ADSP-21990 is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruc-
tion pipeline, and waits for an interrupt. The core clock and
peripheral clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruc-
tion anywhere in code. To exit Idle mode, the DSP responds
to an interrupt and (after two cycles of latency) resumes
executing instructions.
Power down Core Mode
When the ADSP-21990 is in Power Down Core mode, the
DSP core clock is off, but the DSP retains the contents of
the pipeline and keeps the PLL running. The peripheral bus
keeps running, letting the peripherals receive data.
To exit Power Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power Down Core/Peripherals Mode
When the ADSP-21990 is in Power Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off,
but the DSP keeps the PLL running. The DSP does not
retain the contents of the instruction pipeline.The periph-
eral bus is stopped, so the peripherals cannot receive data.
To exit Power Down Core/Peripherals mode, the DSP
responds to an interrupt and (after five to six cycles of
latency) resumes executing instructions.
Power Down All Mode
When the ADSP-21990 is in Power Down All mode, the
DSP core clock, the peripheral clock, and the PLL are all
stopped. The DSP does not retain the contents of the
instruction pipeline. The peripheral bus is stopped, so the
peripherals cannot receive data.
To exit Power Down Core/Peripherals mode, the DSP
responds to an interrupt and (after 500 cycles to re-stabilize
the PLL) resumes executing instructions.
Clock Signals
The ADSP-21990 can be clocked by a crystal oscillator or
a buffered, shaped clock derived from an external clock
oscillator. If a crystal oscillator is used, the crystal should be
connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 5. Capacitor
values are dependent on crystal type and should be specified
by the crystal manufacturer. A parallel resonant, fundamen-
tal frequency, microprocessor grade crystal should be used
for this configuration.
If a buffered, shaped clock is used, this external clock
connects to the DSP’s CLKIN pin. CLKIN input cannot
be halted, changed, or operated below the specified
frequency during normal operation. This clock signal
should be a TTL compatible signal. When an external clock
is used, the XTAL input must be left unconnected.
The DSP provides a user programmable 1؋ to 32؋ multi-
plication of the input clock, including some fractional
values, to support 128 external to internal (DSP core) clock
ratios. The BYPASS pin, and MSEL6–0 and DF bits, in the
PLL configuration register, decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be
12 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA

12 Page





SeitenGesamt 30 Seiten
PDF Download[ ADSP21990 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADSP21990Mixed Signal DSP ControllerAnalog Devices
Analog Devices
ADSP21991Mixed Signal DSP ControllerAnalog Devices
Analog Devices
ADSP21992Mixed Signal DSP ControllerAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche