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AD9511 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9511
Beschreibung 1.2 GHz Clock Distribution IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9511 Datasheet, Funktion
1.2 GHz Clock Distribution IC, PLL Core,
Dividers, Delay Adjust, Five Outputs
AD9511
FEATURES
Low phase noise phase-locked loop core
Reference input frequencies to 250 MHz
Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCPS) extends tuning range
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9511 provides a multi-output clock distribution
function along with an on-chip PLL core. The design
emphasizes low jitter and phase noise to maximize data
converter performance. Other applications with demanding
phase noise and jitter requirements also benefit from this part.
The PLL section consists of a programmable reference divider
(R); a low noise phase frequency detector (PFD); a precision
charge pump (CP); and a programmable feedback divider (N).
By connecting an external VCXO or VCO to the CLK2/CLK2B
pins, frequencies up to 1.6 GHz may be synchronized to the
input reference.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels.
REFIN
REFINB
FUNCTION
CLK1
CLK1B
SCLK
SDIO
SDO
CSB
FUNCTIONAL BLOCK DIAGRAM
VS GND
RSET
CPRSET VCP
DISTRIBUTION
REF
AD9511
SYNCB,
RESETB
PDB
R DIVIDER
N DIVIDER
PHASE
FREQUENCY
DETECTOR
PLL
REF
CHARGE
PUMP
PLL
SETTINGS
SERIAL
CONTROL
PORT
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVDS/CMOS
/1, /2, /3... /31, /32
ΔT
DELAY
ADJUST
LVDS/CMOS
CP
STATUS
CLK2
CLK2B
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B
OUT3
OUT3B
OUT4
OUT4B
Figure 1.
Each output has a programmable divider that may be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output may be varied by means
of a divider phase select function that serves as a coarse timing
adjustment. One of the LVDS/CMOS outputs features a
programmable delay element with full-scale ranges up to 10 ns
of delay. This fine tuning delay block has 5-bit resolution, giving
32 possible delays from which to choose for each full-scale
setting.
The AD9511 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9511 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated by
connecting the charge pump supply (VCP) to 5.5 V. The
temperature range is −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.






AD9511 Datasheet, Funktion
AD9511
Parameter
NOISE CHARACTERISTICS
In-Band Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit
PLL DIGITAL LOCK DETECT WINDOW4
Required to Lock
(Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns Only)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
To Unlock After Lock (Hysteresis)4
Low Range (ABP 1.3 ns, 2.9 ns Only)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Min Typ
Max Unit
Test Conditions/Comments
−172
−156
−149
−142
−218 +
10 × log (fPFD)
3.5
7.5
3.5
7
15
11
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
The synthesizer phase noise floor is
estimated by measuring the in-band
phase noise at the output of the VCO and
subtracting 20logN (where N is the
N divider value).
Approximation of the PFD/CP phase noise
floor (in the flat region) inside the PLL loop
bandwidth. When running closed loop this
phase noise is gained up by 20 × log(N)3.
Signal available at STATUS pin
when selected by 08h<5:2>.
Selected by Register ODh.
ns <5> = 1b.
ns <5> = 0b.
ns <5> = 0b.
Selected by Register 0Dh.
ns <5> = 1b.
ns <5> = 0b.
ns <5> = 0b.
1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.
2 CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section).
3 Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output.
4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK INPUTS
Table 2.
Parameter
CLOCK INPUTS (CLK1, CLK2)1
Input Frequency
Input Sensitivity
Input Level
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Min Typ Max Unit
Test Conditions/Comments
0 1.6 GHz
1502 mV p-p Jitter performance can be improved with higher slew
rates (greater swing).
23 V p-p Larger swings turn on the protection diodes and can
degrade jitter performance.
1.5 1.6 1.7 V
Self-biased; enables ac coupling.
1.3
1.8 V
With 200 mV p-p signal applied; dc-coupled.
150 mV p-p CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
4.0 4.8 5.6 kΩ
Self-biased.
2 pF
1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
2 With a 50 Ω termination, this is −12.5 dBm.
3 With a 50 Ω termination, this is +10 dBm.
Rev. A | Page 5 of 60

6 Page









AD9511 pdf, datenblatt
Parameter
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1-TO-CMOS ADDITIVE PHASE NOISE
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
> 10 MHz Offset
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 78.6432 MHz, OUT = 78.6432 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 78.6432 MHz, OUT = 39.3216 MHz
Divide Ratio = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
AD9511
Min Typ Max Unit
−154
dBc/Hz
−156
dBc/Hz
−158
dBc/Hz
Test Conditions/Comments
Distribution Section only; does not
include PLL or external VCO/VCXO
−110
−121
−130
−140
−145
−149
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−122
−132
−143
−152
−158
−160
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−122
−132
−140
−150
−155
−158
−160
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−136
−146
−155
−161
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 11 of 60

12 Page





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