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DS2153Q Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2153Q
Beschreibung E1 Single-Chip Transceiver
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS2153Q Datasheet, Funktion
www.dalsemi.com
DS2153Q
E1 Single-Chip Transceiver
FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard line interface for clock/data recovery
and waveshaping
32-bit or 128-bit jitter attenuator
Generates line build-outs for both 120-ohm
and 75-ohm lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip
buffers that can connect to backplanes up to
8.192 MHz
8-bit parallel control port that can be used on
either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional
E1, H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to both Si and Sa bits
Three separate loopbacks for testing
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
errors, and E bits
Pin-compatible with DS2151Q T1 Single-
Chip Transceiver
5V supply; low power CMOS
Industrial grade version (-40°C to +85°C)
available (DS2153QN)
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
PARALLEL CONTROL
PORT
DALLAS
DS2153Q
E1 SCT
ACTUAL SIZE OF 44-PIN PLCC
ALE
WR
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
7
8
9
10
11
12
13
14
15
16
17
39 TSER
38 TCLK
37 DVDD
36 TSYNC
35 TLINK
34 TLCLK
33 TCHBLK
32 TRING
31 TVDD
30 TVSS
29 TTIP
DESCRIPTION
The DS2153Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2153 automatically adjusts to E1 22 AWG (0.6 mm) twisted-pair cables from 0 to
1.5 km. The device can generate the necessary G.703 waveshapes for both 75-ohm and 120-ohm cables.
The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit
or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data
stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information.
The device contains a set of 71 8-bit internal registers which the user can access to control the operation
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DS2153Q Datasheet, Funktion
DS2153Q
PIN SYMBOL TYPE
DESCRIPTION
18 RCHBLK
O Receive Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in
applications where not all E1 channels are used, such as Fractional
E1, 384 kbps service (H0), 1920 kbps (H12), or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert
applications. See Section 13 for timing details.
19 ACLKI
I Alternate Clock Input. Upon a receive carrier loss, the clock
applied at this pin (normally 2.048 MHz) will be routed to the
RCLK pin. If no clock is routed to this pin, then it should be tied to
DVSS VIA A 1 kresistor.
20 BTS
21 RTIP
22 RRING
23 RVDD
24 RVSS
25 XTAL1
26 XTAL2
27 INT1
28 INT2
29 TTIP
30 TVSS
31 TVDD
32 TRING
I Bus Type Select. Strap high to select Motorola bus timing; strap
low to select Intel bus timing. This pin controls the function of the
RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins
assume the function listed in parenthesis ().
- Receive Tip and Ring. Analog inputs for clock recovery circuitry;
connects to a 1:1 transformer (see Section 12 for details).
- Receive Analog Positive Supply. 5.0 volts. Should be tied to
DVDD and TVDD pins.
- Receive Signal Ground. 0.0 volts. Should be tied to local ground
plane.
- Crystal Connections. A pullable 8.192 MHz crystal must be
applied to these pins. See Section 12 for crystal specifications.
O Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain
output.
O Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
- Transmit Tip. Analog line driver output; connects to a step-up
transformer (see Section 12 for details).
- Transmit Signal Ground. 0.0 volts. Should be tied to local ground
plane.
- Transmit Analog Positive Supply. 5.0 volts. Should be tied to
DVDD and RVDD pins.
- Transmit Ring. Analog line driver outputs; connects to a step-up
transformer (see Section 12 for details).
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DS2153Q pdf, datenblatt
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
-
TFPT
T16S
TUA1
TSiS
TSA1
TSM
DS2153Q
(LSB)
TSIO
SYMBOL
-
TFPT
T16S
TUA1
TSiS
TSA1
TSM
TSIO
POSITION NAME AND DESCRIPTION
TCR1.7 Not Assigned. Should be set to 0 when written to.
TCR1.6
Transmit Timeslot 0 Pass Through.
0=FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1=FAS bits/Sa bits/Remote Alarm sourced from TSER
TCR1.5
Transmit Timeslot 16 Data Select.
0=sample timeslot 16 at TSER pin
1=source timeslot 16 from TS1 to TS16 registers
TCR1.4
Transmit Unframed All 1s.
0=transmit data normally
1=transmit an unframed all 1’s code at TPOS and TNEG
TCR1.3
Transmit International Bit Select.
0=sample Si bits at TSER pin
1=source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TCR1.2
Transmit Signaling All 1s.
0=normal operation
1=force timeslot 16 in every frame to all 1s
TCR1.1
TSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=CAS and CRC4 multiframe mode (see the timing in Section
13)
TCR1.0
TSYNC I/O Select.
0=TSYNC is an input
1=TSYNC is an output
Note: See Figure 13-9 for more details about how the Transmit Control Registers affect the operation of
the DS2153Q.
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