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EDS2732AABH-6B Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EDS2732AABH-6B
Beschreibung 256M bits SDRAM (8M words x 32 bits)
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
EDS2732AABH-6B Datasheet, Funktion
DATA SHEET
256M bits SDRAM
EDS2732AABH-6B (8M words × 32 bits)
Description
The EDS2732AABH is a 256M bits SDRAM organized
as 2,097,152 words × 32 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 90-ball FBGA.
Features
3.3V power supply
Clock frequency: 166MHz (max.)
Single pulsed /RAS
• ×32 organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8 and full
page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
Address
8K Row address /256 column address
Refresh cycles
4096 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
FBGA package with lead free solder (Sn-Ag-Cu)
Pin Configurations
/xxx indicate active low signal.
90-ball FBGA
123456789
A
DQ26 DQ24 VSS
B
DQ28 VDDQ VSSQ
C
VSSQ DQ27 DQ25
D
VSSQ DQ29 DQ30
E
VDDQ DQ31 NC
F
VSS DQM3 A3
G
A4 A5 A6
H
A7 A8 A12
J
CLK CKE A9
K
DQM1 NC NC
L
VDDQ DQ8 VSS
M
VSSQ DQ10 DQ9
N
VSSQ DQ12 DQ14
P
DQ11 VDDQ VSSQ
R
DQ13 DQ15 VSS
(Top view)
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
A10 A0 A1
NC BA1 A11
BA0 /CS /RAS
/CAS /WE DQM0
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
A0 to A12
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0492E40 (Ver. 4.0)
Date Published February 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005






EDS2732AABH-6B Datasheet, Funktion
EDS2732AABH-6B
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol min.
max.
Unit Test condition
Notes
Input leakage current
Output leakage current
Output high voltage
Output low voltage
ILI
ILO
VOH
VOL
–1
–1.5
2.4
1
1.5
0.4
µA 0 VIN VDD
µA 0 VOUT VDD, DQ = disable
V IOH = –2 mA
V IOL = 2 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter
Symbol Pins
min. typ.
max.
Unit
Input capacitance
CI1 CLK
1.5 —
3.0 pF
Address, CKE, /CS,
CI2 /RAS, /CAS, /WE, 1.5
DQM
3.0 pF
Data input/output
capacitance
CI/O
DQ
3.0 —
5.5 pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
Data Sheet E0492E40 (Ver. 4.0)
6

6 Page









EDS2732AABH-6B pdf, datenblatt
EDS2732AABH-6B
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (A0 to A12). (See
Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and
the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]
The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins
(A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the mode register configuration. After
power on, the contents of the mode register are undefined, execute the mode register set command to set up the
mode register.
Data Sheet E0492E40 (Ver. 4.0)
12

12 Page





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