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PDF PFM19030 Data sheet ( Hoja de datos )
| Número de pieza | PFM19030 | |
| Descripción | 2-Stage Power Module Enhancement-Mode Lateral MOSFETs | |
| Fabricantes | Cree Research | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PFM19030 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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PFM1S9h0e3et04US.PcEomCIFICATION1930-1990 MHz, 30W, 2-Stage Power Module
ataEnhancement-Mode Lateral MOSFETs
.DThis versatile PCS module provides excellent linearity and efficiency in a
wlow-cost surface mount package. The PFM19030 includes two stages of Package Type: Surface Mount
wamplification, along with internal sense FETs that are on the same silicon
w die as the RF devices. These thermally coupled sense FETs simplify the
PN: PFM19030SM
mtask of bias temperature compensation of the overall amplifier. The module
includes RF input, interstage, and output matching elements. The source
oand load impedances required for optimum operation of the module are
.cmuch higher (and simpler to realize) than for unmatched Si LDMOS
transistors of similar performance.
UThe surface mount package base is typically soldered to a conventional
PCB pad with an array of via holes for grounding and thermal sinking
t4of the module. Optimized internal construction supports low FET
echannel temperature for reliable operation.
Package Type: Flange
PN: PFM19030F
e• 28 dB Gain
h• 30 Watts Peak Output Power
S• Internal Sense FETs
ta(for improved bias control)
• IS95 CDMA Performance
5 Watts Average Output Level
20% Power Added Efficiency
–49 dBc ACPR
aModule Schematic Diagram
.DGate 1
wRF IN Lead
Module Substrate
Q1 Die Carrier
Q1
Input
Match
Output
Match
Q2 Die Carrier
Q2
Input
Match
Output
Match
Drain 2
RF OUT
Lead
ww omSense S1 Lead
.cGate 2 Lead
t4USense S2 Lead
eeD1 Lead
S1
S2
taShNote: Additionally, there are 250 KOhm resistors connected in shunt with all leads, to enhance ESD protection.
w.DaPage 1 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
wwhttp://www.cree.com/
Rev. 2
1 page  
PFM19030
Typical Module Performance
T=+25 °C, unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Typical CW 2-Tone Intermods vs. Output Power
-10 IM3L
IM3U
-20
IM5L
-30 IM5U
IM7L
-40 IM7U
-50
-60
-70
30 31 32 33 34 35 36 37 38 39 40 41 42 43
Average Output Power (dBm)
F1=1959.5 MHz, F2=1960.5 MHz
Vsupply = +27 V, Idsq1 = 75 mA, Idsq2=250 mA
Single-Signal IS95 CDMA ACPR & Efficiency
vs Average Output Power (F=1960 MHz)
-20 ACPR(-900 KHz)
-25 ACPR(+900 KHz)
-30 ACPR(-1.25 MHz)
-35 ACPR(+1.25 MHz)
-40 ACPR(-2.75 MHz)
ACPR(+2.75 MHz)
-45 PAE (%)
-50
30
27
24
21
18
15
12
-55 9
-60 6
-65 3
-70
30
31 32 33 34 35 36 37 38
Average CDMA Output Power (dBm)
0
39
2-Tone IMD Rejection vs. Tone Separation
(Peak Envelope Power = 44.5 dBm)
0 IM3L
IM3U
-10 IM5L
IM5U
-20 IM7L
IM7U
-30
-40
-50
-60
0
10 20 30 40
CW Tone Separation (MHz)
50
2 IS95 CDMA Signal IM Distortion
vs. Ave Output Power (F=1955, 1965 MHz)
-20
-25
-30
-35
-40
-45
-50
-55
-60
30
IM3(+15 MHz)
IM3(-15 MHz)
IM5(-25 MHz)
IM5(+25 MHz)
31 32 33 34 35 36 37
CDMA Total Average Power (dBm)
38
F1=1930 MHz, F2=1930.5 MHz to 1980 MHz
Vsupply = +27 V, Idsq1 = 75 mA, Idsq2=250 mA
WCDMA ACLR & Efficiency vs Output
Power (F=1960 MHz, Test Model 1)
-15 28
-20
ACLR(-5 MHz)
-25 ACLR (+5 MHz)
Efficiency
-30
24
20
16
-35 12
-40 8
-45 4
Page 5 of 15
-50
30
31 32 33 34 35 36 37 38
Average WCDMA Output Power (dBm)
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
0
39
Rev. 2
5 Page 
PFM19030
Test Fixture
A metal-backed PCB with clamps for securing the module is used for module electrical testing and for
product demonstration. The fixture is supplied mounted to a finned heat sink. The fixture schematic is
provided on the following page.
This test fixture uses an active bias circuit, which sets the bias circuit through the Sense FETs (configured as
FETs) and applies the derived gate voltage to the associated RF FETs. This assures particular quiescent bias
currents, with accuracy determined by the Sense FET-to-RF FET current ratios.
Page 11 of 15 Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 2
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet PFM19030.PDF ] | |
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