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DS1270Y Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS1270Y
Beschreibung (DS1270AB/Y) 16M Nonvolatile SRAM
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 8 Seiten
DS1270Y Datasheet, Funktion
www.maxim-ic.com
DS1270Y/AB
16M Nonvolatile SRAM
FEATURES
5 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Unlimited write cycles
Low-power CMOS operation
Read and write access times as fast as 70 ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full ±10% VCC operating range (DS1270Y)
Optional ±5% VCC operating range
(DS1270AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
NC
A20
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 VCC
35 A19
34 NC
33 A15
32 A17
31 WE
30 A13
29 A8
28 A9
27 A11
26 OE
25 A10
24 CE
23 DQ7
22 DQ6
21 DQ5
20 DQ4
19 DQ3
36-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
PIN DESCRIPTION
A0 – A20
- Address Inputs
DQ0 - DQ7
- Data In/Data Out
CE - Chip Enable
WE - Write Enable
OE - Output Enable
VCC
GND
- Power (+5V)
- Ground
NC - No Connect
DESCRIPTION
The DS1270 16M Nonvolatile SRAMs are 16,777,216-bit, fully static nonvolatile SRAMs organized as
2,097,152 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
additional support circuitry is required for microprocessor interfacing.
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033104






DS1270Y Datasheet, Funktion
POWER-DOWN/POWER-UP CONDITION
DS1270Y/AB
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
VCC Fail Detect to CE and WE Inactive
tPD
VCC slew from VTP to 0V
tF
VCC slew from 0V to VTP
tR
VCC Valid to CE and WE Inactive
tPU
VCC Valid to End of Write Protection
tREC
MIN
150
150
TYP
(tA: See Note 10)
MAX UNITS NOTES
1.5 µs 11
µs
µs
2 ms
125 ms
PARAMETER
Expected Data Retention Time
SYMBOL MIN TYP
tDR 5
MAX
(tA=25°C)
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
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