(PDF) DP8481 Datasheet - TTL to 10k ECL Level Translator with Latch

Número de pieza	DP8481
Descripción	TTL to 10k ECL Level Translator with Latch
Fabricantes	National Semiconductor
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No Preview Available ! June 1986 DP8481 TTL to 10k ECL Level Translator with Latch General Description This circuit translates TTL input levels to ECL output levels and provides a fall-through latch The outputs are gated with CS providing for wire ORing of outputs The strobe and chip select inputs operate at ECL levels Logic and Connection Diagram Features Y 16-pin flat-pack or DIP Y ECL control inputs Y CS provided for wire ORing of output bus Y 10k ECL I O compatible Y 3 0 ns typical propagation delay Truth Table Dual-In-Line Package D Q STR HL LH XQ XL L L H X Hehigh level (most positive) Lelow level (most negative) Xedon’t care CS H H H L Order Number DP8481F DP8481J or DP8481N See NS Package F16B J16A or N16A Top View TL F 5862 – 1 C1995 National Semiconductor Corporation TL F 5862 RRD-B30M115 Printed in U S A 1 page Physical Dimensions inches (millimeters) Ceramic Flat Package (F) Order Number DP8481F NS Package F16B Ceramic Dual-In-Line Package (J) Order Number DP8481J NS Package J16A 5 5 Page

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PDF DP8481 Data sheet ( Hoja de datos )