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DP8422V Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP8422V
Beschreibung microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
DP8422V Datasheet, Funktion
May 1992
DP8420V 21V 22V-33 DP84T22-25 microCMOS
Programmable 256k 1M 4M Dynamic RAM
Controller Drivers
General Description
The DP8420V 21V 22V-33 DP84T22-25 dynamic RAM
controllers provide a low cost single chip interface between
dynamic RAM and all 8- 16- and 32-bit systems The
DP8420V 21V 22V-33 DP84T22-25 generate all the re-
quired access control signal timing for DRAMs An on-chip
refresh request clock is used to automatically refresh the
DRAM array Refreshes and accesses are arbitrated on
chip If necessary a WAIT or DTACK output inserts wait
states into system access cycles including burst mode ac-
cesses RAS low time during refreshes and RAS precharge
time after refreshes and back to back accesses are guaran-
teed through the insertion of wait states Separate on-chip
precharge counters for each RAS output can be used for
memory interleaving to avoid delayed back to back access-
es because of precharge An additional feature of the
DP8422V DP84T22 is two access ports to simplify dual ac-
cessing Arbitration among these ports and refresh is done
on chip To make board level circuit testing easier the
DP84T22 incorporates TRI-STATE output buffers
Features
Y On chip high precision delay line to guarantee critical
DRAM access timing parameters
Y microCMOS process for low power
Y High capacitance drivers for RAS CAS WE and DRAM
address on chip
Y On chip support for nibble page and static column
DRAMs
Y TRI-STATE outputs (DP84T22 only)
Y Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Y Selection of controller speeds 25 MHz and 33 MHz
Y On board Port A Port B (DP8422V DP84T22 only) re-
fresh arbitration logic
Y Direct interface to all major microprocessors (applica-
tion notes available)
Y 4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
Control
DP8420V
DP8421V
DP8422V
DP84T22
of Pins
(PLCC)
68
68
84
84
of Address
Outputs
9
10
11
11
Largest
DRAM
Possible
256 kbit
1 Mbit
4 Mbit
4 Mbit
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Dual Access and TRI-STATE
Block Diagram
DP8420V 21V 22V DP74T22 DRAM Controller
TRI-STATE is a registered trademark of National Semiconductor Corporation
Staggered RefreshTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11109
FIGURE 1
TL F 11109 – 1
RRD-B30M105 Printed in U S A






DP8422V Datasheet, Funktion
2 0 Signal Descriptions (Continued)
Pin
Name
Device (If Not
Applicable to All)
2 3 REFRESH SIGNALS
RFIP
RFSH
DISRFSH
2 4 PORT A ACCESS SIGNALS
ADS
(ALE)
CS
AREQ
WAIT
(DTACK)
WAITIN
Input
Output
O
I
I
I
I
I
I
O
O
I
Description
REFRESH IN PROGRESS This output is asserted prior to a refresh cycle and is
negated when all the RAS outputs are negated for that refresh
REFRESH This input asserted with DISRFRSH already asserted will request a
refresh If this input is continually asserted the DP8420V 21V 22V DP84T22 will
perform refresh cycles in a burst refresh fashion until the input is negated If RFSH is
asserted with DISRFSH negated the internal refresh address counter is cleared
(useful for burst refreshes)
DISABLE REFRESH This input is used to disable internal refreshes and must be
asserted when using RFSH for externally requested refreshes
ADDRESS STROBE or ADDRESS LATCH ENABLE Depending on programming
this input can function as ADS or ALE In mode 0 the input functions as ALE and
when asserted along with CS causes an internal latch to be set Once this latch is set
an access will start from the positive clock edge of CLK as soon as possible In Mode
1 the input functions as ADS and when asserted along with CS causes the access
RAS to assert if no other event is taking place If an event is taking place RAS will be
asserted from the positive edge of CLK as soon as possible In both cases the low
going edge of this signal latches the bank row and column address if programmed to
do so
CHIP SELECT This input signal must be asserted to enable a Port A access
ACCESS REQUEST This input signal in Mode 0 must be asserted some time after
the first positive clock edge after ALE has been asserted When this signal is
negated RAS is negated for the access In Mode 1 this signal must be asserted
before ADS can be negated When this signal is negated RAS is negated for the
access
WAIT or DTACK This output can be programmed to insert wait states into a CPU
access cycle With R7 negated during programming the output will function as a
WAIT type output In this case the output will be active low to signal a wait condition
With R7 asserted during programming the output will function as DTACK In this
case the output will be negated to signify a wait condition and will be asserted to
signify the access has taken place Each of these signals can be delayed by a
number of positive clock edges or negative clock levels of CLK to increase the
microprocessor’s access cycle through the insertion of wait states
WAIT INCREASE This input can be used to dynamically increase the number of
positive clock edges of CLK until DTACK will be asserted or WAIT will be negated
during a DRAM access
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DP8422V pdf, datenblatt
3 0 Programming and Resetting (Continued)
3 3 PROGRAMMING BIT DEFINITIONS (Continued)
Symbol
R5 R4
00
01
10
11
R3 R2
00
01
10
11
R1 R0
00
01
10
11
Description
WAIT DTACK during Burst (See Section 5 1 2 or 5 2 2)
NO WAIT STATES If R7 e 0 during programming WAIT will remain negated during burst portion of access
If R7 e 1 programming DTACK will remain asserted during burst portion of access
1T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted
WAIT will negate from the positive edge of CLK after the ECASs have been asserted
If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted
DTACK will assert from the positive edge of CLK after the ECASs have been asserted
T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted
WAIT will negate on the negative level of CLK after the ECASs have been asserted
If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted
DTACK will assert from the negative level of CLK after the ECASs have been asserted
0T If R7 e 0 during programming WAIT will assert when the ECAS inputs are negated WAIT will negate when
the ECAS inputs are asserted
If R7 e 1 during programming DTACK will negate when the ECAS inputs are negated DTACK will assert when
the ECAS inputs are asserted
WAIT DTACK Delay Times (See Section 5 1 1 or 5 2 1)
NO WAIT STATES If R7 e 0 during programming WAIT will remain high during non-delayed accesses WAIT
will negate when RAS is negated during delayed accesses
NO WAIT STATES If R7 e 1 during programming DTACK will be asserted when RAS is asserted
T If R7 e 0 during programming WAIT will negate on the negative level of CLK after the access RAS
1T If R7 e 1 during programming DTACK will be asserted on the positive edge of CLK after the access RAS
NO WAIT STATES T If R7 e 0 during programming WAIT will remain high during non-delayed accesses
WAIT will negate on the negative level of CLK after the access RAS during delayed accesses
T If R7 e 1 during programming DTACK will be asserted on the negative level of CLK after the access RAS
1T If R7 e 0 during programming WAIT will negate on the positive edge of CLK after the access RAS
1 T If R7 e 1 during programming DTACK will be asserted on the negative level of CLK after the positive edge
of CLK after the access RAS
RAS Low and RAS Precharge Time
RAS asserted during refresh e 2 positive edges of CLK
RAS precharge time e 1 positive edge of CLK
RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422V DP84T22)
RAS asserted during refresh e 3 positive edges of CLK
RAS precharge time e 2 positive edges of CLK
RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422V DP84T22)
RAS asserted during refresh e 2 positive edges of CLK
RAS precharge time e 2 positive edges of CLK
RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422V DP84T22)
RAS asserted during refresh e 4 positive edges of CLK
RAS precharge time e 3 positive edges of CLK
RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422V DP84T22)
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