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DP8418 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP8418
Beschreibung (DP8417 - DP8419) 64k / 256k Dynamic RAM Controller/Drivers
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 28 Seiten
DP8418 Datasheet, Funktion
PRELIMINARY
August 1989
DP8417 NS32817 8418 32818 8419 32819 8419X
32819X 64k 256k Dynamic RAM Controller Drivers
General Description
The DP8417 8418 8419 8419X represent a family of 256k
DRAM Controller Drivers which are designed to provide
‘‘No-Waitstate’’ CPU interface to Dynamic RAM arrays of up
to 2 Mbytes and larger Each device offers slight functional
variations of the DP8419 design which are tailored for differ-
ent system requirements All family members are fabricated
using National’s new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed level of integration and power
consumption
Each device integrates the following critical 256k DRAM
controller functions on a single monolithic device ultra pre-
cise delay line 9-bit refresh counter fall-through row col-
umn and bank select input latches Row Column address
muxing logic on-board high capacitive-load RAS CAS and
Write Enable Address output drivers and precise control
signal timing for all the above
There are four device options of the basic DP8419 Control-
ler The DP8417 is pin and function compatible with the
DP8419 except that its outputs are TRI-STATE The
DP8418 changes one pin and is specifically designed to
offer an optimum interface to 32 bit microprocessors The
DP8419X is functionally identical to the DP8419 but is avail-
able in a 52-pin DIP package which is upward pin compati-
ble with National’s new DP8429D 1 Mbit DRAM Controller
Driver
Each device is available in plastic DIP Ceramic DIP and
Plastic Chip Carrier (PCC) packaging (Continued)
TRI-STATE is a registered trademark of National Semiconductor Corp
PAL is a registered trademark of and used under license with Monolithic Memories Inc
Operational Features
Y Makes DRAM Interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Y Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Y Eliminates 15 to 20 SSI MSI components for significant
board real estate reduction system power savings and
the elimination of chip-to-chip AC skewing
Y On-board ultra precise delay line
Y On-board high capacitive RAS CAS WE and address
drivers (specified driving 88 DRAMs directly)
Y AC specified for directly addressing up to 8 Megabytes
Y Low power high speed bipolar oxide isolated process
Y Upward pin and function compatible with new DP8428
DP8429 1 Mbit DRAM controller drivers
Y Downward pin and function compatible with DP8408A
DP8409A 64k 256k DRAM controller drivers
Y 4 user selectable modes of operation for Access and
Refresh (2 automatic 2 external)
Contents
Y System and Device Block Diagrams
Y Recommended Companion Components
Y Device Connection Diagrams and Pin Definitions
Y Family Device Differences
(DP8419 vs DP8409A 8417 8418 8419X)
Y Mode of Operation
(Descriptions and Timing Diagrams)
Y Application Description and Diagrams
Y DC AC Electrical Specifications Timing Diagrams and
Test Conditions
System Diagram
C1995 National Semiconductor Corporation TL F 8396
TL F 8396 – 25
RRD-B30M105 Printed in U S A






DP8418 Datasheet, Funktion
Family Device Differences
DP8417 vs DP8419
The DP8417 is identical to the DP8419 with the exception
that its RAS CAS WE and Q (Multiplexed Address) outputs
are TRI-STATE when CS (Chip Select) is high and the chip
is not in a refresh mode This feature allows access to the
same DRAM array through multiple DRAM Controller Driver
DP8417s All AC specifications are the same as the DP8419
except tCSRLO which is 34 ns for the DP8417 versus 5 ns
for the DP8419 Separate delay specifications for the TRI-
STATE timing paths are provided in the AC tables of this
data sheet
DP8418 vs DP8419
The DP8418 DYNAMIC RAM CONTROLLER DRIVER is
identical to the DP8419 with the exception of two functional
differences incorporated to improve performance with 32-bit
microprocessors
1) Pin 26 (B1) is used to enable disable a pair of RAS out-
puts and pin 27 (B0 on the DP8419) is a no connect
When B1 is low RAS0 and RAS1 are enabled such that
they both go low during an access When B1 is high
RAS2 and RAS3 are enabled This feature is useful when
driving words to 32 bits or more since each RAS would
be driving only one half of the word By distributing the
load on each RAS line in this way the DP8418 will meet
the same AC specifications driving 2 banks of 32 DRAMs
each as the DP8419 does driving 4 banks of 16 bits each
2) The hidden refresh function available on the DP8419 has
been disabled in order to reduce the amount of setup
time necessary from CS going low to RASIN going low
during an access of DRAM This parameter called
tCSRL1 is 5 ns for the DP8418 whereas it is 34 ns for the
DP8419 The hidden refresh function only allows a very
small increase in system performance at best at micro-
processor frequencies of 10 MHz and above
DP8419 vs DP8409A
The DP8419 High Speed DRAM Controller Driver combines
the most popular memory control features of the
DP8408A 9A DRAM Controller Driver with the high speed
of bipolar oxide isolation processing
The DP8419 retains the high capacitive-load drive capability
of the DP8408A 9A as well as its most frequently used ac-
cess and refresh modes allowing it to directly replace the
DP8408A 9A in applications using only modes 0 1 4 and 5
Thus the DP8419 will allow most DP8408A 9A users to
directly upgrade their system by replacing their old control-
ler chip with the DP8419
The highest priority of the DP8419 is speed By peforming
the DRAM address multiplexing control signal timing and
high-capacitive drive capability on a single chip propagation
delay skews are minimized Emphasis has been placed on
reducing delay variation over the specified supply and tem-
perature ranges
Except for the following a DP8419 will operate essentially
the same as a DP8409A
1) The DP8419 has significantly faster AC performance
2) The DP8419 can replace the DP8409A in applications
which use modes 0 1 4 and 5 Modes 2 3 6 and 7 of
the DP8409A are not available on the DP8419
3) Pin 4 on the DP8419 is RAHS instead of M1 as on the
DP8409A and allows for two choices of tRAH in mode 5
4) RFI O does not function as an end-of-count signal in
Mode 0 on the DP8419 as it does on the DP8409A
5) DP8419 address and control outputs do not TRI-STATE
when CS is high as on the DP8409A DP8419 control
outputs are active high when CS is high (unless refresh-
ing)
Pin Definitions
VCC GND GND b VCC e 5V g10% The three supply
pins have been assigned to the center of the package to
reduce voltage drops both DC and AC There are two
ground pins to reduce the low level noise The second
ground pin is located two pins from VCC so that decoupling
capacitors can be inserted directly next to these pins It is
important to adequately decouple this device due to the
high switching currents that will occur when all 9 address
bits change in the same direction simultaneously A recom-
mended solution would be a 1 mF multilayer ceramic capaci-
tor in parallel with a low-voltage tantalum capacitor both
connected as close as possible to VCC and GND to reduce
lead inductance See Figure below
TL F 8396 – 4
Capacitor values should be chosen depending on the particular application
R0 – R8 Row Address Inputs
C0 – C8 Column Address Inputs
Q0 – Q8 Multiplexed Address Outputs - This address is
selected from the Row Address Input Latch the Column
Address Input Latch or the Refresh Counter
RASIN Row Address Strobe Input - RASIN directly con-
trols the selected RAS output when in an access mode and
all RAS outputs during hidden or external refresh
R C (RFCK) - In the auto-modes this pin is the external
refresh clock input one refresh cycle should be performed
each clock period In the external access mode it is Row
Column Select Input which enables either the row or column
address input latch onto the output bus
CASIN (RGCK) - In the auto-modes this pin is the RAS
Generator Clock input In external access mode it is the
Column Address Strobe input which controls CAS directly
once columns are enabled on the address outputs
ADS Address (Latch) Strobe Input - Row Address Col-
umn Address and Bank Select Latches are fall-through with
ADS high latching occurs on high-to-low transition of ADS
CS Chip Select Input - When high CS disables all access-
es Refreshing however in both modes 0 and 1 is not af-
fected by this pin
M0 M2 (RFSH) Mode Control Inputs - These pins select
one of the four available operational modes of the DP8419
(see Table III)
RFI O Refresh Input Output - In the auto-modes this pin
is the Refresh Request Output It goes low following RFCK
6

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DP8418 pdf, datenblatt
DP8419 Mode Descriptions (Continued)
The Refresh Request on RFI O is terminated as RAS goes
low This signal may be used to end the refresh earlier than
it normally would as described above If M2 is pulled high
while the RAS lines are low then the RASs go high tRFRH
later The designer must be careful however not to violate
the minimum RAS low time of the DRAMs He must also
guarantee that the minimum RAS precharge time is not vio-
lated during a transition from mode 1 to mode 5 when an
access is desired immediately following a refresh
If the processor tries to access memory while the DP8419 is
in mode 1 WAIT states should be inserted into the proces-
sor cycles until the DP8419 is back in mode 5 and the de-
sired access has been accomplished (see Figure 9 )
Instead of using WAIT states to delay accesses when re-
freshing HOLD states could be used as follows RFRQ
could be connected to a HOLD or Bus Request input to the
system When convenient the system acknowledges the
HOLD or Bus Request by pulling M2 low Using this
scheme HOLD will end as the RAS lines go low (RFI O
goes high) Thus there must be sufficient delay from the
time HOLD goes high to the DP8419 returning to mode 5 so
that the RAS low time of the DRAMs isn’t violated as de-
scribed earlier (see Figure 3 for mode 1 refresh with Hold
states)
To perform a forced refresh the system will be inactive for
about four periods of RGCK For a frequency of 10 MHz
this is 400 ns To refresh 128 rows every 2 ms an average of
about one refresh per 16 ms is required With a RFCK period
of 16 ms and RGCK period of 100 ns DRAM accesses are
delayed due to refresh only 2 5% of the time If using the
Hidden Refresh available in mode 5 (refreshing with RFCK
high) this percentage will be even lower
MODE 4 - EXTERNALLY CONTROLLED ACCESS
In this mode all control signal outputs can be controlled
directly by the corresponding control input The enabled
RAS output follows RASIN CAS follows CASIN (with R C
low) WE follows WIN and R C determines whether the row
or the column inputs are enabled to the address outputs
(see Figure 4 )
With R C high the row address latch contents are enabled
onto the address bus RAS going low strobes the row ad-
dress into the DRAMs After waiting to allow for sufficient
row-address hold time (tRAH) after RAS goes low R C can
go low to enable the column address latch contents onto
the address bus When the column address is valid CAS
going low will strobe it into the DRAMs WIN determines
whether the cycle is a read write or read-modify-write ac-
cess Refer to Figures 5a and 5b for typical Read and Write
timing using mode 4
Resistors required depends on
DRAM load
DRAMs Maybe 16k 64k or 256k
For 4 Banks can drive 16 data bits
a6 Check Bits for ECC
For 2 Banks can drive 32 data bits
a7 Check Bits for ECC
For 1 Bank can drive 64 data bits
a8 Check Bits for ECC
TL F 8396 – 12
FIGURE 4 Typical Application of DP8419 Using External Control Access and Refresh in Modes 0 and 4
12

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