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DP8432V Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP8432V
Beschreibung (DP8430V - DP8432V) microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 30 Seiten
DP8432V Datasheet, Funktion
July 1993
DP8430V 31V 32V-33 microCMOS Programmable
256k 1M 4M Dynamic RAM Controller Drivers
General Description
The DP8430V 31V 32V dynamic RAM controllers provide a
low cost single chip interface between dynamic RAM and
all 8- 16- and 32-bit systems The DP8430V 31V 32V gen-
erate all the required access control signal timing for
DRAMs An on-chip refresh request clock is used to auto-
matically refresh the DRAM array Refreshes and accesses
are arbitrated on chip If necessary a WAIT or DTACK out-
put inserts wait states into system access cycles including
burst mode accesses RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge An additional fea-
ture of the DP8432V is two access ports to simplify dual
accessing Arbitration among these ports and refresh is
done on chip
Features
Y On chip high precision delay line to guarantee critical
DRAM access timing parameters
Y microCMOS process for low power
Y High capacitance drivers for RAS CAS WE and DRAM
address on chip
Y On chip support for nibble page and static column
DRAMs
Y Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Y Can use a single clock source Up to 33 MHz operating
frequency
Y On board Port A Port B (DP8432V only) refresh arbitra-
tion logic
Y Direct interface to all major microprocessors
Y 4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
Control
DP8430V
DP8431V
DP8432V
of Pins
(PLCC)
68
68
84
of Address
Outputs
9
10
11
Largest
DRAM
Possible
256 kbit
1 Mbit
4 Mbit
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Block Diagram
DP8430V 31V 32V DRAM Controller
TRI-STATE is a registered trademark of National Semiconductor Corporation
Staggered RefreshTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11118
FIGURE 1
TL F 11118 – 1
RRD-B30M75 Printed in U S A






DP8432V Datasheet, Funktion
2 0 Signal Descriptions (Continued)
Pin
Name
Device (If not
Applicable to All)
2 3 REFRESH SIGNALS
RFIP
RFSH
2 4 PORT A ACCESS SIGNALS
ADS
(ALE)
CS
AREQ
WAIT
(DTACK)
WAITIN
2 5 PORT B ACCESS SIGNALS
AREQB
DP8432V
only
ATACKB DP8432V
only
Input
Output
O
I
I
I
I
I
O
O
I
I
O
Description
REFRESH IN PROGRESS This output is asserted prior to a refresh cycle and is
negated when all the RAS outputs are negated for that refresh
REFRESH This input asserted will request a refresh If this input is continually
asserted the DP8430V 31V 32V will perform refresh cycles in a burst refresh
fashion until the input is negated
ADDRESS STROBE or ADDRESS LATCH ENABLE Depending on programming
this input can function as ADS or ALE In mode 0 the input functions as ALE and
when asserted along with CS causes an internal latch to be set Once this latch is set
an access will start from the positive clock edge of CLK as soon as possible In Mode
1 the input functions as ADS and when asserted along with CS causes the access
RAS to assert if no other event is taking place If an event is taking place RAS will be
asserted from the positive edge of CLK as soon as possible In both cases the low
going edge of this signal latches the bank row and column address if programmed to
do so
CHIP SELECT This input signal must be asserted to enable a Port A access
ACCESS REQUEST This input signal in Mode 0 must be asserted some time after
the first positive clock edge after ALE has been asserted When this signal is
negated RAS is negated for the access In Mode 1 this signal must be asserted
before ADS can be negated When this signal is negated RAS is negated for the
access
WAIT or DTACK This output can be programmed to insert wait states into a CPU
access cycle With R7 negated during programming the output will function as a
WAIT type output In this case the output will be active low to signal a wait condition
With R7 asserted during programming the output will function as DTACK In this
case the output will be negated to signify a wait condition and will be asserted to
signify the access has taken place Each of these signals can be delayed by a
number of positive clock edges or negative clock levels of CLK to increase the
microprocessor’s access cycle through the insertion of wait states
WAIT INCREASE This input can be used to dynamically increase the number of
positive clock edges of CLK until DTACK will be asserted or WAIT will be negated
during a DRAM access
PORT B ACCESS REQUEST This input asserted will latch the row column and bank
address if programmed and requests an access to take place for Port B If the
access can take place RAS will assert immediately If the access has to be delayed
RAS will assert as soon as possible from a positive edge of CLK
ADVANCED TRANSFER ACKNOWLEDGE PORT B This output is asserted when
the access RAS is asserted for a Port B access This signal can be used to generate
the appropriate DTACK or WAIT type signal for Port B’s CPU or bus
6

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DP8432V pdf, datenblatt
4 0 Port A Access Modes
The DP8430V 31V 32V have two general purpose access
modes Mode 0 RAS synchronous and Mode 1 RAS asyn-
chronous One of these modes is selected at programming
through the B1 input A Port A access to DRAM is initiated
by two input signals ADS (ALE) and CS The access is al-
ways terminated by one signal AREQ These input signals
should be synchronous to the input clock
4 1 ACCESS MODE 0
Mode 0 synchronous access is selected by negating the
input B1 during programming (B1e0) To initiate a Mode 0
access ALE is pulse high and CS is asserted If precharge
time was met a refresh of DRAM or a Port B access was
not in progress the RAS (RASs) would be asserted on the
first rising edge of clock If a refresh or a Port B access is in
progress or precharge time is required the controller will
wait until these events have taken place and assert RAS
(RASs) on the next positive edge of clock
Sometime after the first positive edge of clock after ALE and
CS have been asserted the input AREQ must be asserted
In single port applications once AREQ is asserted CS can
be negated On the other hand ALE can stay asserted sev-
eral periods of clock however ALE must be negated before
or during the period of CLK in which AREQ is negated
The controller samples AREQ on the every rising edge of
clock after DTACK is asserted The access will end when
AREQ is sampled negated
FIGURE 8a Access Mode 0
TL F 11118 – 8
12

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