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DP8440 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP8440
Beschreibung (DP8440 / DP8441) microCMOS Programmable 16/64 Mbit Dynamic RAM Controller/Driver
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 46 Seiten
DP8440 Datasheet, Funktion
February 1995
DP8440-40 DP8440-25 DP8441-40 DP8441-25
microCMOS Programmable 16 64 Mbit
Dynamic RAM Controller Driver
General Description
The DP8440 41 Dynamic RAM Controllers provide an easy
interface between dynamic RAM arrays and 8- 16- 32- and
64-bit microprocessors The DP8440 41 DRAM Controllers
generate all necessary control and timing signals to suc-
cessfully interface and design dynamic memory systems
With significant enhancements over the DP8420 21 22
predecessors the DP8440 41 are suitable for high perform-
ance memory systems These controllers support page and
burst accesses for fast page static column and nibble
DRAMs Refreshes and accesses are arbitrated on chip
RAS low time during refresh and RAS precharge time are
guaranteed by these controllers Separate precharge coun-
ters for each RAS output avoid delayed back to back ac-
cesses due to precharge when using memory interleaving
Programmable features make the DP8440 41 DRAM Con-
trollers flexible enough to fit many memory systems
Features
Y 40 MHz and 25 MHz operation
Y Page detection
Y Automatic CPU burst accesses
Y Support 1 4 16 64 Mbits DRAMs
Y High capacitance drivers for RAS CAS WE and Q out-
puts
Y Support for fast page static column and nibble mode
DRAMs
Y High precision PLL based delay line
Y Byte enable for word size up to 32 bits on the DP8440
or 64 bits on the DP8441
Y Automatic Internal Refresh
Y Staggered RAS-Only refresh
Y Burst and CAS-before-RAS refresh
Y Error scrubbing during refresh
Y TRI-STATE outputs
Y Easy interface to all major microprocessors
Block Diagram
FIGURE 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11718
TL F 11718 – 1
RRD-B30M75 Printed in U S A






DP8440 Datasheet, Funktion
2 0 Functional Introduction
Reset and Programming After the power up the
DP8440 41 must be reset and programmed before it can be
used to access the DRAM The chip is programmed through
the address bus
Initialization Period After programming the DP8440 41
enter a 60 ms initialization period During this time the
DP8440 41 perform refreshes to the DRAM Further warm
up cycles are unnecessary The user must wait until the
initialization is over to access the memory
Modes of Operation The DP8440 41 are synchronous
DRAM controllers Every access is synchronized to the sys-
tem clock The controllers can be programmed in Page
Mode or Normal Mode Burst accesses are dynamically re-
quested through the input BSTARQ
Opening Access They involve a new row address Regard-
less of the access mode programmed opening accesses
behave in the same way ADS and CS initiate and qualify
every access After asserting the ADS the DP8440 41 will
assert RAS from the next rising edge of the CLK The
DP8440 41 will hold the row address on the DRAM address
bus and guarantee that the row address is held for the Row
Address Hold Time (tRAH) programmed The DRAM control-
ler will then switch the internal multiplexor to place the col-
umn address on the DRAM address bus and assert CAS
DTACK will wait the programmed number of wait states be-
fore asserting to indicate the end of the access
Normal Access If the controller is programmed in Normal
Mode (B1 e 1) RAS will assert and negate after the pro-
grammed RAS low time The user can perform burst access
if desired
Page Access The DP8440 41 have an internal page com-
parator This feature enables the user to do a series of ac-
cesses without negating RAS for as long as the row address
remains unchanged The user needs to provide a new ad-
dress for every access The page comparator can also be
programmed as an input This is beneficial for CPUs that
have an internal page comparator The user can do burst
accesses while in page if desired
Burst Access These controllers can also generate new
addresses to burst a specific number of locations The user
can choose to burst in a wrap around fashion for 2 4 8 16
locations Or if the input NoWRAP is asserted the control-
ler will burst consecutive locations and the column address
will not wrap around The controller must be programmed in
Latch Mode to generate the burst addresses
Refresh Modes The DP8440 41 can perform Automatic
Internal Refreshes or Externally Controlled Refreshes Dur-
ing a long page access the controller can queue up to six
refresh requests and burst refresh the addresses missed
when the access finishes
Refresh Types The DP8440 41 can be programmed to do
all RAS Refresh Staggered Refresh Error Scrubbing during
Refresh or CAS-before-RAS refresh
Wait Support These controllers provide wait logic for all
three types of accesses The user needs to program the
desired number of wait states for opening page and burst
accesses
RAS and CAS Configurations The RAS outputs can be
programmed to drive one two or four banks of memory and
the CAS drivers can be programmed for byte writing in bus-
es up to 64 bits wide
TRI-STATE Outputs and Multiporting The GRANT input
can be used for multi-porting When high this input will
TRI-STATE the outputs allowing another controller to drive
the DRAM
Other Features Independent RAS precharge counters al-
low memory interleaving thus back to back access to differ-
ent memory banks is not delayed due to precharge
The output NADTACK can be used to pipeline one address
getting the next access to start one clock early
The input NoWRAP will increment the address during a
burst access in a linear fashion This is convenient for
graphics or long page access
Terminology This paragraph explains the terminology
used in this data sheet The terms negated and asserted are
used For example ECAS0 asserted means the ECAS0 in-
put is at logic 0 The term NoWRAP asserted means that
NoWRAP is at logic 1
6

6 Page









DP8440 pdf, datenblatt
Programming the DP8440 41 (Continued)
4 3 PROGRAMMING SELECTION (Continued)
DIVISOR SELECT
C3 C2 C1 C0
0 0 0 0 20
0 0 0 1 19
0 0 1 0 18
0 0 1 1 17
0 1 0 0 16
0 1 0 1 15
0 1 1 0 14
0 1 1 1 13
1 0 0 0 12
1 0 0 1 11
1 0 1 0 10
10119
11008
11017
11106
11115
RAS AND CAS CONFIGURATIONS AND REFRESH BEHAVIOR
C5 C4
0 0 All RAS and all CAS are selected B0 and B1 are not used All RAS refresh
01
If C6 e 0 Non Error B1
B0 is not Used
Scrubbing Selected All 0 RAS0–1
CAS Selected 2-Step 1 RAS2–3
Staggered Refresh
If C6 e 1 Error
Scrubbing Selected
All RAS Refresh
CAS Pairs Selected
B1 B0 is Not Used
0 RAS0 – 1 and CAS0 – 1 CAS4 – 5
1 RAS2 – 3 and CAS2 – 3 CAS6 – 7
1 0 If C6 e 0 Non Error B1
B0
Scrubbing Selected
All CASs Selected
4-Step Staggered
Refresh
0
0
1
1
0 RAS0
1 RAS1
0 RAS2
1 RAS3
If C6 e 1 Error
B1 B0
Scrubbing Selected
All RAS Refresh
CAS Pairs
Selected
0
0
1
1
0 RAS0 CAS0 – 4
1 RAS1 CAS1 – 5
0 RAS2 CAS2 – 6
1 RAS3 CAS3 – 7
11
If C6 e 0 Non Error
Scrubbing 2-Step
Staggered Refresh
CAS Pairs Selected
B1 B0 is not used
0 RAS0–1 and CAS0 1 4 5
1 RAS2–3 and CAS2 3 6 7
If C6 e 1 Error
Scrubbing Selected
All RAS Refresh
CAS Pairs Selected
B1 B0 is not used
0 RAS0 – 1 and CAS0 1 4 5
1 RAS2 – 3 and CAS2 3 6 7
ERROR SCRUBBING MODE SELECT
C6
0 Staggered Refresh (Non Error Scrubbing)
1 Error Scrubbing (No CAS-before-RAS and No Staggered Refresh)
12

12 Page





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