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PDF DP8459 Data sheet ( Hoja de datos )
| Número de pieza | DP8459 | |
| Descripción | All-Code Data Synchronizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADVANCED
December 1995
DP8459 All-Code Data Synchronizer
General Description
The DP8459 Data Synchronizer is an integrated phase
locked loop circuit which has been designed for application
in magnetic hard disk, flexible (floppy) disk, optical disk, and
tape drive memory systems for data re-synchronization and
clock recovery with any standard recording code, operating
to 25 Mb/s. The DP8459 is provided in a 28-pin PCC
package. Zero phase start is employed during both data and
reference clock lock sequences for rapid acquisition. An
optional (Customer-controlled) synchronization field
frequency-acquisition feature guarantees lock, accommo-
dating the preamble types used with GCR (Group Code
Recording), MFM (Modified Frequency Modulation), the
[1,N] run length limited (RLL) codes, and either of the
standard 2,7 RLL codes. Precise synchronization window
generation is achieved via an internal, self-aligning delay line
which remains accurate independent of temperature, power
supply, external component and IC process variations. The
DP8459 also incorporates a digitally controlled ( MICROW-
IRE™ bus compatible) strobe function with 5-bit resolution
which allows for margin testing, error recovery routines, and
precise window calibration. The PLL filter resides external to
the chip, with two ports provided to allow significant design
flexibility. Synchronization pattern detection circuitry issues a
PREAMBLE DETECTED signal when a pre-determined
length of the user-selected pattern is encountered. All digital
input and output signals are TTL compatible and a single,
+5V power supply is required. The DP8459V is offered as a
DP8459V-10 (250 Kbit/sec thru 10 Mbits/sec) or
DP8459V-25 (250 Kbits/sec thru 25 Mbit/sec), see AC
Electrical Characteristics.
Features
n Fully integrated dual-gain PLL
n Zero phase start lock sequence
n 250 Kbit/sec–25 Mbit/sec data rate range
n Frequency lock capability (optional) for all standard
recording codes
n Digital window strobe control, 5-bit resolution
n Two-port PLL filter network
n PLL free-run (Coast) control for optical disk defects
n Synchronization pattern (preamble lock) detection
n Non-glitching multiplexed read/write clock output
n +5V supply
n DP8459 supplied in 28-pin plastic chip carrier (PCC)
and 40-pin TapePak packages
Connection Diagrams
TL/F/9322-6
FIGURE 1. DP8459 in 28-Pin Plastic Chip Carrier (PCC) V-Type Package Order Number DP8459V-10 or DP8459V-25
TapePak® is a registered trademark of National Semiconductor Corporation.
MICROWIRE™ is a trademark of National Semiconductor Corporation.
© 1996 National Semiconductor Corporation TL/F/9322
http:\\www.national.com
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PrintDate=1996/07/31 PrintTime=11:05:38 ds009322 Rev. No. 1 Proof
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1 page  
1.0 Pin Descriptions (Continued)
Pin #
TTL LEVEL LOGIC OUTPUTS
21 SYNCHRONIZED DATA (SD): A reconstructed replica of the ENCODED READ DATA signal,
time-stabilized and synchronized to the SYNCHRONIZED CLOCK output.
22 PUMP UP (PU): Active HIGH whenever the phase comparator issues a pump-up signal to the charge
pump. The PU pin is an open-emitter output requiring an external passive pull down resistor whenever in
active use. The output should be allowed to float when not needed.
23 PUMP DOWN (PD): Active HIGH whenever the phase comparator issues a pump-down signal to the
charge pump. The PD pin is an open-emitter output requiring an external passive pull down resistor
whenever in active use. The output should be allowed to float when not needed.
ANALOG SIGNAL PINS
28 CHARGE PUMP OUTPUT: The output of the high-speed, switching bi-directional current source circuitry of
the charge pump. The external, passive PLL filter network is established between this pin, the VCO INPUT
pin, and ground.
1 VCO INPUT: The high-impedance control voltage input to the voltage controlled oscillator (VCO). The
external, passive PLL filter network is established between this pin, the CHARGE PUMP OUTPUT pin, and
ground.
2 TIMING EXTRACTOR FILTER: A pin for the connection of external, passive components employed to
stabilize the delay line timing extraction circuitry. Delay accuracy is not a function of external component
values or tolerances.
25 RNOMINAL: A resistor is tied between this pin and VCC to set the charge pump nominal operating current.
The current is internally multiplied by 2 for charge pump use.
26 RBOOST: A resistor is tied between this pin and VCC to set the charge pump boost (or adder) current. The
RBOOST resistor is effectively paralleled with the RNOMINAL resistor when the HIGH GAIN DISABLE input is
inactive (logical-zero); thus the sum of the resistor currents sets the total input current. The input current is
multiplied by 2 within the charge pump circuitry.
Note 1: These pins should always be tied together; they are not intended to be used with separate power supplies.
2.0 Circuit Operation
In the non-Read mode, the DP8459 PLL is locked to the
REFERENCE CLOCK signal. This permits the VCO to remain
at a frequency very close to the encoded data clock rate while
the PLL is “idling” and thus will minimize the frequency step
and associated lock time encountered at the initiation of lock to
ENCODED READ DATA. Frequency acquisition is employed
in the non-Read mode to ensure lock.
Note: The REFERENCE CLOCK signal is employed by circuitry which sets the
time delay of the internal delay line. This requires the REFERENCE CLOCK
signal to be present at all times at a stable and accurate frequency for proper
DP8459 operation.
At the assertion of READ GATE, which is allowed to be done
asynchronously (no timing requirements), and following the
completion of two subsequent VCO cycles, the DP8459 VCO
is stopped momentarily and restarted in accurate phase
alignment with the second data bit which arrives following the
VCO pause. This minimization of phase misalignment
between the ENCODED READ DATA and the VCO (referred to
as zero phase start, or ZPS) significantly reduces data lock
acquisition time.
The DP8459 incorporates a preamble-specific frequency
acquisition feature which may be employed at the user’s
option. The frequency acquisition feature is intended
specifically for use within hard or pseudo-hard sectored
systems where READ GATE is asserted only within a
preamble. With the READ GATE active (logical-one) and the
FREQUENCY LOCK CONTROL (FLC) input active
(logical-zero), the DP8459 will be forced to lock to the exact
preamble frequency selected at the SYNC PATTERN SELECT
inputs. The frequency discriminating action of the PLL
provided in this mode produces a lock-in range equivalent to
the available VCO operating range and thus eliminates the
possibility of fractional-harmonic lock. Windowing (pulse gate
action; see Pulse Gate, Section 2.1) is not employed in the
frequency acquisition mode and thus quadrature lock is
prevented (see National Semiconductor Application Note
AN-414, APPS Mass Storage Handbook #1, 1986, for an
explanation of typical false lock modes). The DP8459 will
remain in the frequency acquisition mode until the FLC input is
deactivated (logical-one). In ordinary hard sectored or
pseudo-hard sectored operation, the PREAMBLE DETECTED
(PDT) output is tied to the FLC input for automatic switching
from frequency acquisition to phase lock following internal
detection of the selected preamble by the DP8459. The
Customer may choose to intervene in this path and extend the
frequency lock period. However, the DP8459 must be placed
in the phase lock mode (FLC deactivated—logical-one) prior
to encountering the end of the preamble, or loss of lock will
result. Switching of the FLC input may be done
asynchronously (no set-up or hold timing requirements).
The PREAMBLE DETECTED (PDT) output will become active
(logical-one) following READ GATE assertion, completion of
the ZPS sequence and the subsequent detection of
approximately 32 ENCODED READ DATA (ERD) pulses of the
1T, 2T or 3T preamble types, or 16 ENCODED READ DATA
(ERD) pulses of the 4T preamble type (see specification
tables), and will remain active (logical-one) until deassertion of
READ GATE.
The Customer has the option of employing an elevated PLL
bandwidth during preamble acquisition (or at any other time)
for an extended capture range. An RBOOST pin is provided to
http:\\www.national.com
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PrintDate=1996/07/31 PrintTime=11:05:41 ds009322 Rev. No. 1 Proof
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5 Page 
FIGURE 8. Capture of Early-Shifted ENCODED READ DATA Pulse
TL/F/9322-13
TL/F/9322-14
FIGURE 9. Capture of Late-Shifted ENCODED READ DATA Pulse
DELAY LINE
The DP8459 employs an internal silicon delay line to establish
synchronization window alignment. The delay is nominally
equivalent to one half of the period of the REFERENCE
CLOCK waveform, and is variable in fine increments via the
Control Register in order to achieve the window strobe
function. The Timing Extractor circuitry derives realtive timing
information soley from the REFERENCE CLOCK signal and
regulates the magnitude of the delay within the Delay Line.
http:\\www.national.com
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PrintDate=1996/07/31 PrintTime=11:05:49 ds009322 Rev. No. 1 Proof
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP8459.PDF ] | |
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