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PDF DP8406 Data sheet ( Hoja de datos )
| Número de pieza | DP8406 | |
| Descripción | 32-Bit Parallel Error Detection and Correction Circuit | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 1991
DP8406 (54F 74F632)
32-Bit Parallel Error Detection and Correction Circuit
General Description
The DP8406 device is a 32-bit parallel error detection and
correction circuit (EDAC) in a 52-pin or 68-pin package The
EDAC uses a modified Hamming code to generate a 7-bit
check word from a 32-bit data word This check word is
stored along with the data word during the memory write
cycle During the memory read cycle the 39-bit words from
memory are processed by the EDAC to determine if errors
have occurred in memory
Single-bit errors in the 32-bit data word are flagged and cor-
rected
Single-bit errors in the 7-bit check word are flagged and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location
Dual-bit errors are flagged but not corrected These errors
may occur in any two bits of the 39-bit word from memory
(two errors in the 32-bit data word two errors in the 7-bit
check word or one error in each word) The gross-error
condition of all LOWs or all HIGHs from memory will be
detected Otherwise errors in three or more bits of the
39-bit word are beyond the capabilities of these devices to
detect
Read-modify-write (byte-control) operations can be per-
formed by using output latch enable LEDBO and the indi-
vidual OEB0 through OEB3 byte control pins
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
Data Bit and Check Bit input latches These will determine if
the failure occurred in memory or in the EDAC
Features
Y Detects and corrects single-bit errors
Y Detects and flags dual-bit errors
Y Built-in diagnostic capability
Y Fast write and read cycle processing times
Y Byte-write capability
Y Guaranteed 4000V minimum ESD protection
Y Fully pin and function compatible with
SN74ALS632A thru SN74ALS635 series
TI’s
Simplified Functional Block
Device
DP8406
DP8406
Package
52-Pin
68-Pin
Byte-Write
yes
yes
Output
TRI-STATE
TRI-STATE
FAST and TRI-STATE are registered trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9579
TL F 9579 – 9
RRD-B30M105 Printed in U S A
1 page  
Functional Description (Continued)
TABLE IV Read Flag and Correct Function
Memory
Cycle
EDAC
Function
Control
S1 S0
Data I O
DB Output
DB Control
Latch
OEBn
LEDBO
Check I O
CB
Control
OECB
Error Flags
ERR MERR
Read
Read
Read Flag
Latch Input
Data Check
Bits
H L Input
Latched
H H Input
Data
H
H
X Input
H Enabled (Note 1)
Latched
L Input
H Enabled (Note 1)
Check Word
Read
Output
Corrected Data
Syndrome Bits
H
Output
H Corrected
Data Word
L
Output
X Syndrome
L Enabled (Note 1)
Bits (Note 2)
Note 1 See Table III for error description
Note 2 See Table V for error location
TABLE V Syndrome Decoding
Syndrome Bits
6543210
Error
LLLLLLL
LLL L LLH
LLL L LHL
L L L L LHH
unc
2-Bit
2-Bit
unc
LLL LHLL
2-Bit
LLL LHLH
unc
L L L L HHL
unc
L L L L H H H 2-Bit (Note 2)
LLLHLLL
L L LHL LH
L L LHLHL
L L L H LHH
2-Bit
unc
DB31
2-Bit
L L LHHL L
L L LHHLH
L L L HHHL
L L L HHHH
LLHL LLL
LLHL LLH
LLHL LHL
L LH L LHH
unc
2-Bit
2-Bit
DB30
2-Bit
unc
DB29
2-Bit
L LHLHL L
L LHLHLH
L LH L HHL
L LH L HHH
L LHHL L L
L LHHL LH
L LHHLHL
L LHH LHH
L LHHHL L
L LHHHLH
L LHHHHL
L LHHHHH
DB28
2-Bit
2-Bit
DB27
DB26
2-Bit
2-Bit
DB25
2-Bit
DB24
unc
2-Bit
Syndrome Bits
Error
6543210
L H L L L L L 2-Bit
L H L L L L H unc
L H L L L H L DB7
L H L L L H H 2-Bit
L H L L H L L DB6
L H L L H L H 2-Bit
L H L L H H L 2-Bit
L H L L H H H DB5
L H L H L L L DB4
L H L H L L H 2-Bit
L H L H L H L 2-Bit
L H L H L H H DB3
L H L H H L L 2-Bit
L H L H H L H DB2
L H L H H H L unc
L H L H H H H 2-Bit
L H H L L L L DB0
L H H L L L H 2-Bit
L H H L L H L 2-Bit
L H H L L H H unc
L H H L H L L 2-Bit
L H H L H L H DB1
L H H L H H L unc
L H H L H H H 2-Bit
L H H H L L L 2-Bit
L H H H L L H unc
L H H H L H L unc
L H H H L H H 2-Bit
L H H H H L L unc
L H H H H L H 2-bit
L H H H H H L 2-bit
L H H H H H H CB6
CBX e Error in check bit X
DBY e Error in data bit Y
2-Bit e Double-bit error
unc e Uncorrectable multi-bit error
Note 2-bit and unc condition will cause both ERR and MERR to be LOW
Note 1 Syndrome bits for all LOWs MERR and ERR LOW for all LOWs
only ERR LOW for DB30 error
Note 2 Syndrome bits for all HIGHs
5
5 Page 
AC Electrical Characteristics
Symbol
Parameter
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
DB or CB to ERR
Propagation Delay
DB to ERR
Propagation Delay
DB or CB to MERR
Propagation Delay
DB to MERR
Propagation Delay
S0 and S1 LOW to DB
Propagation Delay
S1 to CB
Propagation Delay
S0 or S1 to ERR or MERR
Propagation Delay
DB to CB
Propagation Delay
LEDBO to DB
Output Enable Time
OEBn to DB
Output Disable Time
OEBn to DB
Output Enable Time
OECB to CB
Output Disable Time
OECB to CB
74F
TA e a25 C
VCC e a5 0V
CL e 50 pF
Min Typ Max
4 0 14 0 27 0
4 0 10 5 18 0
4 0 21 0 27 0
4 0 14 0 18 0
5 0 17 0 27 0
5 0 16 0 27 0
5 0 23 0 27 0
5 0 19 0 27 0
4 0 12 0 16 0
4 0 12 0 16 0
4 0 10 5 14 0
4 0 9 0 14 0
2 0 11 5 13 0
4 0 16 0 23 0
4 0 18 0 23 0
2 0 11 0 13 0
2 0 11 0 13 0
1 0 6 0 10 0
1 0 6 0 10 0
10 5 0 10 0
1 0 4 0 10 0
1 0 6 0 10 0
1 0 6 0 10 0
1 0 5 0 10 0
1 0 4 0 10 0
54F
TA VCC e Mil
CL e 50 pF
Min Max
74F
TA VCC e Com
CL e 50 pF
Min Max
4 0 31 0
4 0 20 0
4 0 31 0
4 0 20 0
5 0 31 0
5 0 31 0
5 0 31 0
5 0 31 0
4 0 20 0
4 0 20 0
4 0 15 0
4 0 15 0
2 0 14 0
4 0 25 0
4 0 25 0
2 0 14 0
2 0 14 0
1 0 10 0
1 0 10 0
1 0 10 0
1 0 10 0
1 0 10 0
1 0 10 0
1 0 10 0
1 0 10 0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DP8406.PDF ] | |
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