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EP20K100E Schematic ( PDF Datasheet ) - Altera

Teilenummer EP20K100E
Beschreibung (APEP20K Series) Programmable Logic Device Family
Hersteller Altera
Logo Altera Logo 




Gesamt 30 Seiten
EP20K100E Datasheet, Funktion
March 2004, ver. 5.1
APEX 20K
Programmable Logic
Device Family
Data Sheet
Features
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
– MultiCoreTM architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
– LUT logic used for register-intensive functions
– Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
– ESB implementation of product-term logic used for
combinatorial-intensive functions
High density
– 30,000 to 1.5 million typical gates (see Tables 1 and 2)
– Up to 51,840 logic elements (LEs)
– Up to 442,368 RAM bits that can be used without reducing
available logic
– Up to 3,456 product-term-based macrocells
Table 1. APEX 20K Device Features Note (1)
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
EP20K30E EP20K60E
113,000 162,000
30,000
1,200
12
24,576
192
128
60,000
2,560
16
32,768
256
196
EP20K100
263,000
100,000
4,160
26
53,248
416
252
EP20K100E EP20K160E
263,000
404,000
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
EP20K200
526,000
200,000
8,320
52
106,496
832
382
EP20K200E
526,000
200,000
8,320
52
106,496
832
376
Altera Corporation
DS-APEX20K-5.1
1






EP20K100E Datasheet, Funktion
APEX 20K Programmable Logic Device Family Data Sheet
General
Description
APEXTM 20K devices are the first PLDs designed with the MultiCore
architecture, which combines the strengths of LUT-based and product-
term-based devices with an enhanced memory structure. LUT-based logic
provides optimized performance and efficiency for data-path, register-
intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths,
such as complex state machines. LUT- and product-term-based logic
combined with memory functions and a wide variety of MegaCore and
AMPP functions make the APEX 20K device architecture uniquely suited
for system-on-a-programmable-chip designs. Applications historically
requiring a combination of LUT-, product-term-, and memory-based
devices can now be integrated into one APEX 20K device.
APEX 20KE devices are a superset of APEX 20K devices and include
additional features such as advanced I/O standard support, CAM,
additional global clocks, and enhanced ClockLock clock circuitry. In
addition, APEX 20KE devices extend the APEX 20K family to 1.5 million
gates. APEX 20KE devices are denoted with an “E” suffix in the device
name (e.g., the EP20K1000E device is an APEX 20KE device). Table 8
compares the features included in APEX 20K and APEX 20KE devices.
6 Altera Corporation

6 Page









EP20K100E pdf, datenblatt
APEX 20K Programmable Logic Device Family Data Sheet
Each LAB contains dedicated logic for driving control signals to its LEs
and ESBs. The control signals include clock, clock enable, asynchronous
clear, asynchronous preset, asynchronous load, synchronous clear, and
synchronous load signals. A maximum of six control signals can be used
at a time. Although synchronous load and clear signals are generally used
when implementing counters, they can also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked (e.g., any LE in a particular LAB
using CLK1 will also use CLKENA1). LEs with the same clock but different
clock enable signals either use both clock signals in one LAB or are placed
into separate LABs.
If both the rising and falling edges of a clock are used in a LAB, both LAB-
wide clock signals are used.
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack Interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Dedicated
Clocks
2 or 4 (1)
Global
Signals
4
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
SYNCLOAD
or LABCLKENA2
LABCLKENA1
LABCLR1 (2)
SYNCCLR
or LABCLK2 (3)
LABCLK1
LABCLR2 (2)
Notes to Figure 4:
(1) APEX 20KE devices have four dedicated clocks.
(2) The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(3) The SYNCCLR signal can be generated by the local interconnect or global signals.
12 Altera Corporation

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