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PDF GT-6816 Data sheet ( Hoja de datos )
| Número de pieza | GT-6816 | |
| Descripción | SCANNER Chips | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de GT-6816 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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m GT-6816
.coI. General Descriptions-
t4UThe GT-6816 is an enhanced version of GT-6801, which provides highly integrated System-On-Chip
ee(SOC) solution for high-performance color scanner. The GT-6816 is enhanced not only in the AFE
h(Analog Front End) from 12-bit to 16-bit but also built-in an intelligent power management circuit to
taSmeet both operating and suspend mode for USB bus-powered Scanner. The GT-6816 is also pin to pin
abackward compatible with the GT-6801, providing system designer easy way to upgrade the current
www.Dapplications without changing the hardware design.
II. Features-
² Single-chip integration for high-performance color scanner application
m² On-chip Analog Front End: CDS/AGC and 16-bit ADC Maximum 6MHz
o² On-chip universal TG supports various types of CCD/CIS sensors
² Embedded high-performance RISC controller
.c² On-chip USB transceiver
² Built-in 16KB image line buffers
² PC interface supports : USB/EPP/ECP/BPP
U² No external memory component required for typical application
² Firmware programmable frame size
t4² Intelligent power management meets both operating and suspend mode for USB
bus power
e² On-chip PLL circuits
² Operating clock :48 MHz with external crystal: 6 MHz
e² Operating voltage: Core: 3.3V, I/O: 5V
h² Operating current: Core 80mA, AFE 50mA
² Suspend current: 50 A
S² Package: 128-QFP & 44-QFP
taAFE
.DaCDS
PGA
16-bit ADC
Compression
Engine
www6MHz
PLL
Universal
Timing
Scanner
Image Buffer
Crystal
MOTOR
Generator
Control Logic
eet4U.comI/O RISC
Program
memory
Mask
ROM
Intelligent
Power
Management
PC interface
Parallel port
ECP
EPP
SPP
USB
taShROM
www.Da2KB
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GT-6816
DACK
DERR
DSLC
GNDI1
GNDI2
DPE
DSLCIN
DINIT
DAFD
DSTRB
VDDI1
PD0
PD1
PD2
PD3
GNDC4
PD4
PD5
PD6
VDDC4
PD7
HBUSY
VDDI2
VDDI3
HACK
HERR
HSLC
VDDI4
HPE
HSLCIN
HINIT
GNDI3
HAFD
HSTRB
GNDI4
SDA
SCL
TEST
GNDU
D-
D+
VDDU
Low
Low
Low
Low
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Low
Low
Low
Low
Low
Tri-state
Tri-state
I Device parallel port (Ack) signal, with
I Device parallel port (Fault) signal
I Device parallel port (select) signal, with
P IO ground
P IO ground
I Device parallel port (Paper end) signal,
O 24mA Device parallel port (Select in) signal
O 24mA Device parallel port (Init) signal
O 24mA Device parallel port (Auto feed) signal
O 24mA Device parallel port (Strobe) signal
P IO power
I/O 24mA Parallel port data bus bit 0, with
I/O 24mA Parallel port data bus bit 1, with
I/O 24mA Parallel port data bus bit 2, with
I/O 24mA Parallel port data bus bit 3, with
P Core ground
I/O 24mA Parallel port data bus bit 4, with
I/O 24mA Parallel port data bus bit 5, with
I/O 24mA Parallel port data bus bit 6, with
P Core power,
I/O 24mA Parallel port data bus bit 7, with
O 24mA Host parallel port (Busy) signal
P I/O Power
P I/O Power
O 24mA Host parallel port (Ack) signal
O 24mA Host parallel port (Fault) signal, with
O 24mA Host parallel port (Select) signal
P I/O power
O 24mA Host parallel port (Paper end) signal
I Host parallel port (Select in) signal, with
I Host parallel port (Init) signal, with
P I/O ground
I Host parallel port (Auto feed) signal,
I Host parallel port (Strobe) signal, with
P I/O ground
I/O 4mA Serial EEPROM data line, PCB need
I/O 4mA Serial EEPROM clock line, PCB need
I For test only, with pull-down, not
P USB transceiver ground
I/O USB transceiver D-
I/O USB transceiver D+
P USB transceiver power
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5 Page 
GT-6816
Name
R/W Address Description
UDCRR1 R ‘hffD9 USB Device Command Receive Register 1
UDCRR2 R ‘hffDA USB Device Command Receive Register 2
UDCRR3 R ‘hffDB USB Device Command Receive Register 3
UDCRR4 R ‘hffDC USB Device Command Receive Register 4
UDCRR5 R ‘hffDD USB Device Command Receive Register 5
UDCRR6 R ‘hffDE USB Device Command Receive Register 6
UDCRR7 R ‘hffDF USB Device Command Receive Register 7
l Registers Definitions
l Timing Generator Setup Register
CPU Read/Write
Address: FF00H
Bit Reset Description
7:4 4’b0 Reserved
Select LED control signal output to PEPP_AD0~PEPP_AD2 for the sake
of driving issue.
When this bit is set, the mapping of pins are changed to:
PTGR = TG_R,
PTGG = TG_G,
PTGB = TG_B,
3 1’b0
PEPP_AD0 = LED_R,
PEPP_AD1 = LED_G,
PEPP_AD2 = LED_B;
Note: TG_R, TG_G, TG_B are TG signal for R, G, B channel.
LED_R, LED_G, LED_B are LED signal for R, G, B channel.
These signals are programmable by register definitions.
TG rise event enable :
0 = disable TG rise event.
2 1’b1
1 = enable TG rise event. TG event will occur when TG signal changes
state from ‘0’ to ‘1’
Sensor type :
0 = CIS
1 1’b0 1 = CCD
As select in CIS mode, PH1 will output TG signal and controlled by
H1_pol and H1_en.
0 1’b0 Global Timing Generator enable control.
11
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| PDF Descargar | [ Datasheet GT-6816.PDF ] | |
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