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CDB8421 Schematic ( PDF Datasheet ) - Cirrus Logic

Teilenummer CDB8421
Beschreibung 32-bit / 192 kHz Asynchronous Sample Rate Converter
Hersteller Cirrus Logic
Logo Cirrus Logic Logo 




Gesamt 30 Seiten
CDB8421 Datasheet, Funktion
CS8421
32-bit, 192 kHz Asynchronous Sample Rate Converter
Features
z 175 dB Dynamic Range
z –140 dB THD+N
z No Programming Required
z No External Master Clock Required
z Supports Sample Rates up to 211 kHz
z Input/Output Sample Rate Ratios from 7.5:1
to 1:8
z Master Clock Support for 128 x fs, 256 x fs,
384 x fs, and 512 x fs (Master Mode)
z 16, 20, 24, or 32-bit Data I/O
z 32-bit Internal Signal Processing
z Dither Automatically Applied and Scaled to
Output Resolution
I
z Flexible 3-Wire Serial Digital Audio Input and
Output Ports
z Master and Slave Modes for Both Input and
Output
z Bypass Mode
z Time Division Multiplexing (TDM) Mode
z Attenuates Clock Jitter
z Multiple Part Outputs are Phase Matched
z Linear Phase FIR Filter
z Automatic Soft Mute/Unmute
z +2.5 V Digital Supply (VD)
z +3.3 V or 5.0 V Digital Interface (VL)
z Space Saving 20-pin TSSOP and QFN
Packages
RST
Level Translators
BYPASS
SDIN
ISCLK
ILRCK
Serial
Audio
Data
Input
Sync Info
Time
Varying
Digital
Filters
Data
Sync Info
MS_SEL
SAIF
SAOF
Serial
Port
Mode
Decoder
Digital
PLL
3.3 V or 5.0 V (VL)
2.5 V (VD) GND
Serial
Data Audio
Output
Clock
Generator
XTI XTO
TDM_IN
SDOUT
OSCLK
OLRCK
SRC_UNLOCK
MCLK_OUT
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
JAN ‘05
DS641PP1
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CDB8421 Datasheet, Funktion
CS8421
PERFORMANCE SPECIFICATIONS (XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS,
Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits, unless otherwise stated.)
Parameter
Min
Resolution
16
Sample Rate with XTI = 27.000 MHz
Slave 7.2
Master 53
Sample Rate with other XTI clocks
Slave XTI/3750
Master XTI/512
Sample Rate with ring oscillator (XTI to GND or VL, XTO floating)
12
Sample Rate Ratio - Upsampling
-
Sample Rate Ratio - Downsampling
-
Interchannel Gain Mismatch
-
Interchannel Phase Deviation
-
Peak Idle Channel Noise Component (32-bit operation)
-
Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input)
44.1 kHz:48 kHz
A-Weighted
Unweighted
-
-
44.1 kHz:192 kHz
A-Weighted
Unweighted
-
-
48 kHz:44.1 kHz
A-Weighted
Unweighted
-
-
48 kHz:96 kHz
A-Weighted
Unweighted
-
-
96 kHz:48 kHz
A-Weighted
Unweighted
-
-
192 kHz:32 kHz
A-Weighted
Unweighted
-
-
Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS
Input)
32 kHz:48 kHz
-
44.1 kHz:48 kHz
-
44.1 kHz:192 kHz
-
48 kHz:44.1 kHz
-
48 kHz:96 kHz
-
96 kHz:48 kHz
-
192 kHz:32 kHz
-
Typ
-
-
-
-
-
-
-
-
0.0
0.0
-
180
177
175
172
180
177
179
176
176
173
175
172
-161
-171
-130
-160
-148
-168
-173
Max Units
32 bits
207 kHz
211 kHz
XTI/130 kHz
XTI/128 kHz
96 kHz
1:8
7.5:1
- dB
- Degrees
-192 dBFS
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
DIGITAL FILTER CHARACTERISTICS
Parameter
Passband (Upsampling or Downsampling)
Passband Ripple
Stopband
Stopband Attenuation
Group Delay
Min Typ Max Units
- - 0.4535*Fso Hz
- - ±0.007 dB
0.5465*Fso -
125 -
- Hz
- dB
(Note 3)
ms
Notes: 3. The equation for the group delay through the sample rate converter is (56.581 / Fsi) + (55.658 / Fso).
For example, if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay
through the sample rate converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds.
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CDB8421 pdf, datenblatt
CS8421
3. GENERAL DESCRIPTION
The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample rate converter.
The digital audio data is input and output through configurable 3-wire serial ports. The digital audio in-
put/output ports offer Left Justified, Right Justified, and I²S serial audio formats. The CS8421 also sup-
ports a TDM mode which allows multiple channels of digital audio data on one serial line. A bypass mode
allows the data to be passed directly to the output port without sample rate conversion.
The CS8421 does not require a control port interface, helping to speed design time by not requiring the
user to develop software to configure the part. Pins that are sensed after reset allow the part to be con-
figured. See “Reset, Power Down, and Start-up” on page 32.
Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR),
digital mixing consoles, high quality D/A, effects processors and computer audio systems.
Figure 5 and Figure 6 show the supply and external connections to the CS8421.
4. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT
A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the at-
tached device through the MS_SEL, SAIF, and SAOF pins. Table 1, Table 2, and Table 3 show the pin
functions and their corresponding settings. The following parameters are adjustable:
• Master or slave.
• Master clock (MCLK) ratios of 128*Fsi/o, 256*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master mode).
• Audio data resolution of 16, 20, 24, or 32-bits.
• Left or right justification of the data relative to left/right clock (LRCK) as well as I²S.
Figure 7, Figure 8, and Figure 9 show the input/output formats available.
In master mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin mas-
ter clock.
In slave mode, the left/right clock and the serial bit clock are inputs and may be asynchronous to the XTI
master clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough
serial clocks are present in each phase to clock all of the data bits.
ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to
64*Fso. In TDM slave mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s con-
nected together. In TDM master mode, OSCLK is set to 256*Fso
5. MODE SELECTION
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes
of operation. After reset the resistor value and condition (VL or GND) are sensed. This operation will take
approximately 4 µs to complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be mut-
ed until the mode detection sequence has completed. After this, if all clocks are stable, SRC_UNLOCK
will be brought low when audio output is valid and normal operation will occur. Table 1, Table 2, and
Table 3 show the pin functions and their corresponding settings. If the 1.0 koption is selected for
MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a direct connection to VL
or GND as appropriate.
The resistor attached to each mode selection pin should be placed physically close to the CS8421. The
end of the resistor not connected to the mode selection pins should be connected as close as possible to
VL and GND to minimize noise. Table 1, Table 2, and Table 3 show the pin functions and their corre-
sponding settings.
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